| Line 1... |
Line 1... |
--Require Modelsim
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--Require Modelsim
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--Tested on Modelsim 6.5b Revison 2009.05
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--Tested on Modelsim 6.5b Revison 2009.05
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puts {
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puts {
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ModelSimSE SD_HOST_CONTROLLER compile script version 1.1
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ModelSimSE SD_HOST_CONTROLLER compile script version 1.1
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Copyright (c) Doulos June 2004, SD
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Copyright (c) Doulos June 2004,
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Modifed 2010, Adam Edvardsson, ORSoC
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}
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}
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# Simply change the project settings in this section
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# Simply change the project settings in this section
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# for each new project. There should be no need to
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# for each new project. There should be no need to
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# modify the rest of the script.
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# modify the rest of the script.
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set library_file_list {
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set library_file_list {
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design_library {
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design_library {
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../../../rtl/sdc_dma/verilog/SD_defines.v
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../../../rtl/sdc_dma/verilog/sd_defines.v
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../../../rtl/sdc_dma/verilog/SD_Bd.v
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../../../rtl/sdc_dma/verilog/sd_bd.v
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../../../rtl/sdc_dma/verilog/SD_clock_divider.v
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../../../rtl/sdc_dma/verilog/sd_clock_divider.v
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../../../rtl/sdc_dma/verilog/SD_cmd_master.v
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../../../rtl/sdc_dma/verilog/sd_cmd_master.v
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../../../rtl/sdc_dma/verilog/SD_cmd_serial_host.v
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../../../rtl/sdc_dma/verilog/sd_cmd_serial_host.v
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../../../rtl/sdc_dma/verilog/SD_controller_top.v
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../../../rtl/sdc_dma/verilog/sdc_controller.v
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../../../rtl/sdc_dma/verilog/SD_controller_wb.v
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../../../rtl/sdc_dma/verilog/sd_controller_wb.v
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../../../rtl/sdc_dma/verilog/SD_crc_7.v
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../../../rtl/sdc_dma/verilog/sd_crc_7.v
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../../../rtl/sdc_dma/verilog/SD_crc_16.v
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../../../rtl/sdc_dma/verilog/sd_crc_16.v
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../../../rtl/sdc_dma/verilog/SD_data_host.v
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../../../rtl/sdc_dma/verilog/sd_data_serial_host.v
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../../../rtl/sdc_dma/verilog/SD_data_master.v
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../../../rtl/sdc_dma/verilog/sd_data_master.v
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../../../rtl/sdc_dma/verilog/SD_FIFO_RX_Filler.v
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../../../rtl/sdc_dma/verilog/sd_fifo_rx_filler.v
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../../../rtl/sdc_dma/verilog/SD_FIFO_TX_Filler.v
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../../../rtl/sdc_dma/verilog/sd_fifo_tx_filler.v
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}
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}
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test_library { ../../../bench/sdc_dma/verilog/wb_model_defines.v
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test_library { ../../../bench/sdc_dma/verilog/wb_model_defines.v
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../../../bench/sdc_dma/verilog/SD_controller_top_tb.v
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../../../bench/sdc_dma/verilog/sd_controller_top_tb.v
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../../../bench/sdc_dma/verilog/sdModel.v
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../../../bench/sdc_dma/verilog/sdModel.v
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../../../bench/sdc_dma/verilog/timescale.v
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../../../bench/sdc_dma/verilog/timescale.v
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../../../bench/sdc_dma/verilog/wb_bus_mon.v
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../../../bench/sdc_dma/verilog/wb_bus_mon.v
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../../../bench/sdc_dma/verilog/wb_master32.v
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../../../bench/sdc_dma/verilog/wb_master32.v
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../../../bench/sdc_dma/verilog/wb_master_behavioral.v
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../../../bench/sdc_dma/verilog/wb_master_behavioral.v
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../../../bench/sdc_dma/verilog/wb_slave_behavioral.v
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../../../bench/sdc_dma/verilog/wb_slave_behavioral.v
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../../../rtl/sdc_dma/verilog/SD_defines.v
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../../../rtl/sdc_dma/verilog/sd_defines.v
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../../../rtl/sdc_dma/verilog/SD_Bd.v
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../../../rtl/sdc_dma/verilog/sd_bd.v
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../../../rtl/sdc_dma/verilog/SD_clock_divider.v
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../../../rtl/sdc_dma/verilog/sd_clock_divider.v
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../../../rtl/sdc_dma/verilog/SD_cmd_master.v
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../../../rtl/sdc_dma/verilog/sd_cmd_master.v
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../../../rtl/sdc_dma/verilog/SD_cmd_serial_host.v
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../../../rtl/sdc_dma/verilog/sd_cmd_serial_host.v
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../../../rtl/sdc_dma/verilog/SD_controller_top.v
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../../../rtl/sdc_dma/verilog/sdc_controller.v
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../../../rtl/sdc_dma/verilog/SD_controller_wb.v
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../../../rtl/sdc_dma/verilog/sd_controller_wb.v
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../../../rtl/sdc_dma/verilog/SD_crc_7.v
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../../../rtl/sdc_dma/verilog/sd_crc_7.v
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../../../rtl/sdc_dma/verilog/SD_crc_16.v
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../../../rtl/sdc_dma/verilog/sd_crc_16.v
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../../../rtl/sdc_dma/verilog/SD_data_host.v
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../../../rtl/sdc_dma/verilog/sd_data_serial_host.v
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../../../rtl/sdc_dma/verilog/SD_data_master.v
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../../../rtl/sdc_dma/verilog/sd_data_master.v
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../../../rtl/sdc_dma/verilog/SD_FIFO_RX_Filler.v
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../../../rtl/sdc_dma/verilog/sd_fifo_rx_filler.v
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../../../rtl/sdc_dma/verilog/SD_FIFO_TX_Filler.v
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../../../rtl/sdc_dma/verilog/sd_fifo_tx_filler.v
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../../../rtl/sdc_dma/verilog/fifo/smii_rx_fifo.v
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../../../rtl/sdc_dma/verilog/sd_rx_fifo.v
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../../../rtl/sdc_dma/verilog/fifo/smii_tx_fifo.v
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../../../rtl/sdc_dma/verilog/sd_tx_fifo.v
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}
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}
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}
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}
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set top_level test_library.SD_controller_top_tb
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set top_level test_library.sd_controller_top_tb
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set wave_patterns {
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set wave_patterns {
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/*
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/*
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| Line 120... |
Line 121... |
foreach {radix signals} $wave_radices {
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foreach {radix signals} $wave_radices {
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foreach signal $signals {
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foreach signal $signals {
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catch {property wave -radix $radix $signal}
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catch {property wave -radix $radix $signal}
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}
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}
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}
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}
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if $tk_ok {wm geometry .wave [winfo screenwidth .]x330+0-20}
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# if $tk_ok {wm geometry .wave [winfo screenwidth .]x330+0-20}
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}
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}
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# Run the simulation
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# Run the simulation
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when {/SD_controller_top_tb/succes = 1} {stop}
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when {/sd_controller_top_tb/succes = 1} {stop}
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run -all
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run -all
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# If waves are required
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# If waves are required
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if [llength $wave_patterns] {
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if [llength $wave_patterns] {
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