| Line 84... |
Line 84... |
x2b_act_ok, // OK to do an activate
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x2b_act_ok, // OK to do an activate
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x2b_rdok, // OK to do a read
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x2b_rdok, // OK to do a read
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x2b_wrok, // OK to do a write
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x2b_wrok, // OK to do a write
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/* xfr msb address */
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/* xfr msb address */
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sdr_dev_config,
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xfr_bank_sel,
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xfr_bank_sel,
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xfr_addr_msb,
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sdr_req_norm_dma_last,
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sdr_req_norm_dma_last,
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/* SDRAM Timing */
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/* SDRAM Timing */
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tras_delay, // Active to precharge delay
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tras_delay, // Active to precharge delay
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trp_delay, // Precharge to active delay
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trp_delay, // Precharge to active delay
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| Line 133... |
Line 131... |
input x2b_refresh, x2b_act_ok, x2b_rdok,
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input x2b_refresh, x2b_act_ok, x2b_rdok,
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x2b_wrok;
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x2b_wrok;
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input [3:0] tras_delay, trp_delay, trcd_delay;
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input [3:0] tras_delay, trp_delay, trcd_delay;
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input [1:0] sdr_dev_config;
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input [1:0] xfr_bank_sel;
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input [1:0] xfr_bank_sel;
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output [13:0] xfr_addr_msb;
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/****************************************************************************/
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/****************************************************************************/
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// Internal Nets
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// Internal Nets
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wire [3:0] r2i_req, i2r_ack, i2x_req,
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wire [3:0] r2i_req, i2r_ack, i2x_req,
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| Line 561... |
Line 557... |
/* address for current xfr, debug only */
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/* address for current xfr, debug only */
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wire [11:0] cur_row = (xfr_bank_sel==3) ? bank3_row:
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wire [11:0] cur_row = (xfr_bank_sel==3) ? bank3_row:
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(xfr_bank_sel==2) ? bank2_row:
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(xfr_bank_sel==2) ? bank2_row:
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(xfr_bank_sel==1) ? bank1_row: bank0_row;
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(xfr_bank_sel==1) ? bank1_row: bank0_row;
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assign xfr_addr_msb = (sdr_dev_config == 2'b11) ? {cur_row, xfr_bank_sel[1:0]}:
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{cur_row, xfr_bank_sel[0]};
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endmodule // sdr_bank_ctl
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endmodule // sdr_bank_ctl
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No newline at end of file
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No newline at end of file
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