| Line 95... |
Line 95... |
trcd_delay); // Active to R/W delay
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trcd_delay); // Active to R/W delay
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parameter APP_AW = 30; // Application Address Width
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parameter APP_AW = 30; // Application Address Width
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parameter APP_DW = 32; // Application Data Width
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parameter APP_DW = 32; // Application Data Width
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parameter APP_BW = 4; // Application Byte Width
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parameter APP_BW = 4; // Application Byte Width
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parameter APP_RW = 9; // Application Request Width
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_BW = 2; // SDR Byte Width
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parameter SDR_BW = 2; // SDR Byte Width
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parameter REQ_BW = 12; // Request Width
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input clk, reset_n;
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input clk, reset_n;
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input [1:0] a2b_req_depth;
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input [1:0] a2b_req_depth;
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/* Req from bank_ctl */
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/* Req from bank_ctl */
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| Line 110... |
Line 110... |
r2b_write, r2b_wrap;
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r2b_write, r2b_wrap;
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input [`SDR_REQ_ID_W-1:0] r2b_req_id;
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input [`SDR_REQ_ID_W-1:0] r2b_req_id;
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input [1:0] r2b_ba;
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input [1:0] r2b_ba;
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input [11:0] r2b_raddr;
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input [11:0] r2b_raddr;
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input [11:0] r2b_caddr;
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input [11:0] r2b_caddr;
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input [APP_RW-1:0] r2b_len;
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input [REQ_BW-1:0] r2b_len;
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output b2r_arb_ok, b2r_ack;
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output b2r_arb_ok, b2r_ack;
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input sdr_req_norm_dma_last;
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input sdr_req_norm_dma_last;
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/* Req to xfr_ctl */
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/* Req to xfr_ctl */
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output b2x_idle, b2x_req, b2x_start, b2x_last,
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output b2x_idle, b2x_req, b2x_start, b2x_last,
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b2x_tras_ok, b2x_wrap;
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b2x_tras_ok, b2x_wrap;
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output [`SDR_REQ_ID_W-1:0] b2x_id;
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output [`SDR_REQ_ID_W-1:0] b2x_id;
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output [1:0] b2x_ba;
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output [1:0] b2x_ba;
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output [11:0] b2x_addr;
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output [11:0] b2x_addr;
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output [APP_RW-1:0] b2x_len;
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output [REQ_BW-1:0] b2x_len;
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output [1:0] b2x_cmd;
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output [1:0] b2x_cmd;
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input x2b_ack;
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input x2b_ack;
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/* Status from xfr_ctl */
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/* Status from xfr_ctl */
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input [3:0] x2b_pre_ok;
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input [3:0] x2b_pre_ok;
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| Line 139... |
Line 139... |
// Internal Nets
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// Internal Nets
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wire [3:0] r2i_req, i2r_ack, i2x_req,
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wire [3:0] r2i_req, i2r_ack, i2x_req,
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i2x_start, i2x_last, i2x_wrap, tras_ok;
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i2x_start, i2x_last, i2x_wrap, tras_ok;
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wire [11:0] i2x_addr0, i2x_addr1, i2x_addr2, i2x_addr3;
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wire [11:0] i2x_addr0, i2x_addr1, i2x_addr2, i2x_addr3;
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wire [APP_RW-1:0] i2x_len0, i2x_len1, i2x_len2, i2x_len3;
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wire [REQ_BW-1:0] i2x_len0, i2x_len1, i2x_len2, i2x_len3;
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wire [1:0] i2x_cmd0, i2x_cmd1, i2x_cmd2, i2x_cmd3;
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wire [1:0] i2x_cmd0, i2x_cmd1, i2x_cmd2, i2x_cmd3;
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wire [`SDR_REQ_ID_W-1:0] i2x_id0, i2x_id1, i2x_id2, i2x_id3;
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wire [`SDR_REQ_ID_W-1:0] i2x_id0, i2x_id1, i2x_id2, i2x_id3;
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reg b2x_req;
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reg b2x_req;
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wire b2x_idle, b2x_start, b2x_last, b2x_wrap;
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wire b2x_idle, b2x_start, b2x_last, b2x_wrap;
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wire [`SDR_REQ_ID_W-1:0] b2x_id;
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wire [`SDR_REQ_ID_W-1:0] b2x_id;
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wire [11:0] b2x_addr;
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wire [11:0] b2x_addr;
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wire [APP_RW-1:0] b2x_len;
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wire [REQ_BW-1:0] b2x_len;
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wire [1:0] b2x_cmd;
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wire [1:0] b2x_cmd;
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wire [3:0] x2i_ack;
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wire [3:0] x2i_ack;
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reg [1:0] b2x_ba;
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reg [1:0] b2x_ba;
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reg [`SDR_REQ_ID_W-1:0] curr_id;
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reg [`SDR_REQ_ID_W-1:0] curr_id;
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