| Line 98... |
Line 98... |
parameter APP_DW = 32; // Application Data Width
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parameter APP_DW = 32; // Application Data Width
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parameter APP_BW = 4; // Application Byte Width
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parameter APP_BW = 4; // Application Byte Width
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_BW = 2; // SDR Byte Width
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parameter SDR_BW = 2; // SDR Byte Width
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// 12 bit subtractor is not feasibile for FPGA, so changed to 8 bits
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parameter REQ_BW = (`TARGET_DESIGN == `FPGA) ? 8 : 12; // Request Width
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input clk, reset_n;
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input clk, reset_n;
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input [1:0] a2b_req_depth;
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input [1:0] a2b_req_depth;
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/* Req from bank_ctl */
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/* Req from bank_ctl */
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| Line 111... |
Line 109... |
r2b_write, r2b_wrap;
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r2b_write, r2b_wrap;
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input [`SDR_REQ_ID_W-1:0] r2b_req_id;
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input [`SDR_REQ_ID_W-1:0] r2b_req_id;
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input [1:0] r2b_ba;
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input [1:0] r2b_ba;
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input [11:0] r2b_raddr;
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input [11:0] r2b_raddr;
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input [11:0] r2b_caddr;
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input [11:0] r2b_caddr;
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input [REQ_BW-1:0] r2b_len;
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input [`REQ_BW-1:0] r2b_len;
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output b2r_arb_ok, b2r_ack;
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output b2r_arb_ok, b2r_ack;
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input sdr_req_norm_dma_last;
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input sdr_req_norm_dma_last;
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/* Req to xfr_ctl */
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/* Req to xfr_ctl */
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output b2x_idle, b2x_req, b2x_start, b2x_last,
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output b2x_idle, b2x_req, b2x_start, b2x_last,
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b2x_tras_ok, b2x_wrap;
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b2x_tras_ok, b2x_wrap;
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output [`SDR_REQ_ID_W-1:0] b2x_id;
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output [`SDR_REQ_ID_W-1:0] b2x_id;
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output [1:0] b2x_ba;
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output [1:0] b2x_ba;
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output [11:0] b2x_addr;
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output [11:0] b2x_addr;
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output [REQ_BW-1:0] b2x_len;
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output [`REQ_BW-1:0] b2x_len;
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output [1:0] b2x_cmd;
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output [1:0] b2x_cmd;
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input x2b_ack;
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input x2b_ack;
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/* Status from xfr_ctl */
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/* Status from xfr_ctl */
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input [3:0] x2b_pre_ok;
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input [3:0] x2b_pre_ok;
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| Line 140... |
Line 138... |
// Internal Nets
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// Internal Nets
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wire [3:0] r2i_req, i2r_ack, i2x_req,
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wire [3:0] r2i_req, i2r_ack, i2x_req,
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i2x_start, i2x_last, i2x_wrap, tras_ok;
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i2x_start, i2x_last, i2x_wrap, tras_ok;
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wire [11:0] i2x_addr0, i2x_addr1, i2x_addr2, i2x_addr3;
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wire [11:0] i2x_addr0, i2x_addr1, i2x_addr2, i2x_addr3;
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wire [REQ_BW-1:0] i2x_len0, i2x_len1, i2x_len2, i2x_len3;
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wire [`REQ_BW-1:0] i2x_len0, i2x_len1, i2x_len2, i2x_len3;
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wire [1:0] i2x_cmd0, i2x_cmd1, i2x_cmd2, i2x_cmd3;
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wire [1:0] i2x_cmd0, i2x_cmd1, i2x_cmd2, i2x_cmd3;
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wire [`SDR_REQ_ID_W-1:0] i2x_id0, i2x_id1, i2x_id2, i2x_id3;
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wire [`SDR_REQ_ID_W-1:0] i2x_id0, i2x_id1, i2x_id2, i2x_id3;
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reg b2x_req;
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reg b2x_req;
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wire b2x_idle, b2x_start, b2x_last, b2x_wrap;
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wire b2x_idle, b2x_start, b2x_last, b2x_wrap;
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wire [`SDR_REQ_ID_W-1:0] b2x_id;
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wire [`SDR_REQ_ID_W-1:0] b2x_id;
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wire [11:0] b2x_addr;
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wire [11:0] b2x_addr;
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wire [REQ_BW-1:0] b2x_len;
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wire [`REQ_BW-1:0] b2x_len;
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wire [1:0] b2x_cmd;
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wire [1:0] b2x_cmd;
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wire [3:0] x2i_ack;
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wire [3:0] x2i_ack;
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reg [1:0] b2x_ba;
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reg [1:0] b2x_ba;
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reg [`SDR_REQ_ID_W-1:0] curr_id;
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reg [`SDR_REQ_ID_W-1:0] curr_id;
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| Line 229... |
Line 227... |
(rank_ba[7:6] == 2'b00) ? i2x_req[0] & ~i2x_cmd0[1] :
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(rank_ba[7:6] == 2'b00) ? i2x_req[0] & ~i2x_cmd0[1] :
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(rank_ba[7:6] == 2'b01) ? i2x_req[1] & ~i2x_cmd1[1] :
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(rank_ba[7:6] == 2'b01) ? i2x_req[1] & ~i2x_cmd1[1] :
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(rank_ba[7:6] == 2'b10) ? i2x_req[2] & ~i2x_cmd2[1] :
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(rank_ba[7:6] == 2'b10) ? i2x_req[2] & ~i2x_cmd2[1] :
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i2x_req[3] & ~i2x_cmd3[1];
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i2x_req[3] & ~i2x_cmd3[1];
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always @ (rank_req or rank_ba or xfr_ba or xfr_ba_last) begin
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always @ (*) begin
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b2x_req = 1'b0;
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b2x_ba = xfr_ba;
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if(`TARGET_DESIGN == `ASIC) begin // Support Multiple Rank request only on ASIC
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if (rank_req[0]) begin
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if (rank_req[0]) begin
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b2x_req = 1'b1;
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b2x_req = 1'b1;
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b2x_ba = xfr_ba;
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b2x_ba = xfr_ba;
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end // if (rank_req[0])
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end // if (rank_req[0])
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else if (rank_req[1]) begin
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else if (rank_req[1]) begin
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b2x_req = 1'b1;
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b2x_req = 1'b1;
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b2x_ba = rank_ba[3:2];
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b2x_ba = rank_ba[3:2];
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end // if (rank_req[1])
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end // if (rank_req[1])
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else if (rank_req[2]) begin
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else if (rank_req[2]) begin
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b2x_req = 1'b1;
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b2x_req = 1'b1;
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b2x_ba = rank_ba[5:4];
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b2x_ba = rank_ba[5:4];
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end // if (rank_req[2])
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end // if (rank_req[2])
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else if (rank_req[3]) begin
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else if (rank_req[3]) begin
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b2x_req = 1'b1;
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b2x_req = 1'b1;
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b2x_ba = rank_ba[7:6];
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b2x_ba = rank_ba[7:6];
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end // if (rank_req[3])
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end // if (rank_req[3])
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end else begin // If FPGA
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else begin
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if (rank_req[0]) begin
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b2x_req = 1'b0;
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b2x_req = 1'b1;
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b2x_ba = 2'b00;
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end
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end // else: !if(rank_req[3])
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end
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end // always @ (rank_req or rank_fifo_mt or r2b_ba or rank_ba)
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end // always @ (rank_req or rank_fifo_mt or r2b_ba or rank_ba)
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assign b2x_idle = rank_fifo_mt;
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assign b2x_idle = rank_fifo_mt;
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assign b2x_start = i2x_start[b2x_ba];
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assign b2x_start = i2x_start[b2x_ba];
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assign b2x_last = i2x_last[b2x_ba];
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assign b2x_last = i2x_last[b2x_ba];
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