/*********************************************************************
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/*********************************************************************
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SDRAM Controller Bank Controller
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SDRAM Controller Bank Controller
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This file is part of the sdram controller project
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This file is part of the sdram controller project
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http://www.opencores.org/cores/sdr_ctrl/
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http://www.opencores.org/cores/sdr_ctrl/
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Description:
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Description:
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This module takes requests from sdrc_req_gen, checks for page hit/miss and
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This module takes requests from sdrc_req_gen, checks for page hit/miss and
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issues precharge/activate commands and then passes the request to sdrc_xfr_ctl.
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issues precharge/activate commands and then passes the request to sdrc_xfr_ctl.
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To Do:
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To Do:
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nothing
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nothing
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Author(s):
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Author(s):
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- Dinesh Annayya, dinesha@opencores.org
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- Dinesh Annayya, dinesha@opencores.org
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Version : 1.0 - 8th Jan 2012
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Version : 1.0 - 8th Jan 2012
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Copyright (C) 2000 Authors and OPENCORES.ORG
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Copyright (C) 2000 Authors and OPENCORES.ORG
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This source file may be used and distributed without
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This source file may be used and distributed without
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restriction provided that this copyright statement is not
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restriction provided that this copyright statement is not
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removed from the file and that any derivative work contains
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removed from the file and that any derivative work contains
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the original copyright notice and the associated disclaimer.
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the original copyright notice and the associated disclaimer.
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This source file is free software; you can redistribute it
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This source file is free software; you can redistribute it
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and/or modify it under the terms of the GNU Lesser General
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and/or modify it under the terms of the GNU Lesser General
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Public License as published by the Free Software Foundation;
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Public License as published by the Free Software Foundation;
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either version 2.1 of the License, or (at your option) any
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either version 2.1 of the License, or (at your option) any
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later version.
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later version.
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This source is distributed in the hope that it will be
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This source is distributed in the hope that it will be
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useful, but WITHOUT ANY WARRANTY; without even the implied
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useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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PURPOSE. See the GNU Lesser General Public License for more
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PURPOSE. See the GNU Lesser General Public License for more
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details.
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details.
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You should have received a copy of the GNU Lesser General
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You should have received a copy of the GNU Lesser General
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Public License along with this source; if not, download it
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Public License along with this source; if not, download it
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from http://www.opencores.org/lgpl.shtml
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from http://www.opencores.org/lgpl.shtml
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*******************************************************************/
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*******************************************************************/
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`include "sdrc.def"
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`include "sdrc_define.v"
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module sdrc_bank_fsm (clk,
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module sdrc_bank_fsm (clk,
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reset_n,
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reset_n,
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/* Req from req_gen */
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/* Req from req_gen */
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r2b_req, // request
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r2b_req, // request
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r2b_req_id, // ID
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r2b_req_id, // ID
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r2b_start, // First chunk of burst
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r2b_start, // First chunk of burst
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r2b_last, // Last chunk of burst
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r2b_last, // Last chunk of burst
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r2b_wrap,
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r2b_wrap,
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r2b_raddr, // row address
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r2b_raddr, // row address
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r2b_caddr, // col address
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r2b_caddr, // col address
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r2b_len, // length
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r2b_len, // length
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r2b_write, // write request
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r2b_write, // write request
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b2r_ack,
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b2r_ack,
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sdr_dma_last,
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sdr_dma_last,
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/* Transfer request to xfr_ctl */
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/* Transfer request to xfr_ctl */
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b2x_req, // Request to xfr_ctl
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b2x_req, // Request to xfr_ctl
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b2x_start, // first chunk of transfer
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b2x_start, // first chunk of transfer
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b2x_last, // last chunk of transfer
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b2x_last, // last chunk of transfer
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b2x_wrap,
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b2x_wrap,
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b2x_id, // Transfer ID
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b2x_id, // Transfer ID
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b2x_addr, // row/col address
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b2x_addr, // row/col address
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b2x_len, // transfer length
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b2x_len, // transfer length
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b2x_cmd, // transfer command
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b2x_cmd, // transfer command
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x2b_ack, // command accepted
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x2b_ack, // command accepted
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/* Status to/from xfr_ctl */
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/* Status to/from xfr_ctl */
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tras_ok, // TRAS OK for this bank
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tras_ok, // TRAS OK for this bank
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xfr_ok,
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xfr_ok,
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x2b_refresh, // We did a refresh
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x2b_refresh, // We did a refresh
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x2b_pre_ok, // OK to do a precharge (per bank)
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x2b_pre_ok, // OK to do a precharge (per bank)
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x2b_act_ok, // OK to do an activate
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x2b_act_ok, // OK to do an activate
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x2b_rdok, // OK to do a read
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x2b_rdok, // OK to do a read
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x2b_wrok, // OK to do a write
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x2b_wrok, // OK to do a write
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/* current xfr row address of the bank */
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/* current xfr row address of the bank */
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bank_row,
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bank_row,
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/* SDRAM Timing */
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/* SDRAM Timing */
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tras_delay, // Active to precharge delay
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tras_delay, // Active to precharge delay
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trp_delay, // Precharge to active delay
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trp_delay, // Precharge to active delay
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trcd_delay); // Active to R/W delay
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trcd_delay); // Active to R/W delay
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parameter APP_AW = 30; // Application Address Width
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parameter APP_AW = 30; // Application Address Width
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parameter APP_DW = 32; // Application Data Width
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parameter APP_DW = 32; // Application Data Width
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parameter APP_BW = 4; // Application Byte Width
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parameter APP_BW = 4; // Application Byte Width
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parameter APP_RW = 9; // Application Request Width
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parameter APP_RW = 9; // Application Request Width
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_BW = 2; // SDR Byte Width
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parameter SDR_BW = 2; // SDR Byte Width
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input clk, reset_n;
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input clk, reset_n;
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/* Req from bank_ctl */
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/* Req from bank_ctl */
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input r2b_req, r2b_start, r2b_last,
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input r2b_req, r2b_start, r2b_last,
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r2b_write, r2b_wrap;
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r2b_write, r2b_wrap;
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input [`SDR_REQ_ID_W-1:0] r2b_req_id;
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input [`SDR_REQ_ID_W-1:0] r2b_req_id;
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input [11:0] r2b_raddr;
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input [11:0] r2b_raddr;
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input [11:0] r2b_caddr;
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input [11:0] r2b_caddr;
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input [APP_RW-1:0] r2b_len;
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input [APP_RW-1:0] r2b_len;
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output b2r_ack;
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output b2r_ack;
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input sdr_dma_last;
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input sdr_dma_last;
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/* Req to xfr_ctl */
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/* Req to xfr_ctl */
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output b2x_req, b2x_start, b2x_last,
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output b2x_req, b2x_start, b2x_last,
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tras_ok, b2x_wrap;
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tras_ok, b2x_wrap;
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output [`SDR_REQ_ID_W-1:0] b2x_id;
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output [`SDR_REQ_ID_W-1:0] b2x_id;
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output [11:0] b2x_addr;
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output [11:0] b2x_addr;
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output [APP_RW-1:0] b2x_len;
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output [APP_RW-1:0] b2x_len;
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output [1:0] b2x_cmd;
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output [1:0] b2x_cmd;
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input x2b_ack;
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input x2b_ack;
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/* Status from xfr_ctl */
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/* Status from xfr_ctl */
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input x2b_refresh, x2b_act_ok, x2b_rdok,
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input x2b_refresh, x2b_act_ok, x2b_rdok,
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x2b_wrok, x2b_pre_ok, xfr_ok;
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x2b_wrok, x2b_pre_ok, xfr_ok;
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input [3:0] tras_delay, trp_delay, trcd_delay;
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input [3:0] tras_delay, trp_delay, trcd_delay;
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output [11:0] bank_row;
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output [11:0] bank_row;
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/****************************************************************************/
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/****************************************************************************/
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// Internal Nets
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// Internal Nets
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`define BANK_IDLE 3'b000
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`define BANK_IDLE 3'b000
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`define BANK_PRE 3'b001
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`define BANK_PRE 3'b001
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`define BANK_ACT 3'b010
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`define BANK_ACT 3'b010
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`define BANK_XFR 3'b011
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`define BANK_XFR 3'b011
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`define BANK_DMA_LAST_PRE 3'b100
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`define BANK_DMA_LAST_PRE 3'b100
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reg [2:0] bank_st, next_bank_st;
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reg [2:0] bank_st, next_bank_st;
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wire b2x_start, b2x_last;
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wire b2x_start, b2x_last;
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reg l_start, l_last;
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reg l_start, l_last;
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reg b2x_req, b2r_ack;
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reg b2x_req, b2r_ack;
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wire [`SDR_REQ_ID_W-1:0] b2x_id;
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wire [`SDR_REQ_ID_W-1:0] b2x_id;
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reg [`SDR_REQ_ID_W-1:0] l_id;
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reg [`SDR_REQ_ID_W-1:0] l_id;
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reg [11:0] b2x_addr;
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reg [11:0] b2x_addr;
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reg [APP_RW-1:0] l_len;
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reg [APP_RW-1:0] l_len;
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wire [APP_RW-1:0] b2x_len;
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wire [APP_RW-1:0] b2x_len;
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reg [1:0] b2x_cmd;
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reg [1:0] b2x_cmd;
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reg bank_valid;
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reg bank_valid;
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reg [11:0] bank_row;
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reg [11:0] bank_row;
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reg [3:0] tras_cntr, timer0;
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reg [3:0] tras_cntr, timer0;
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reg l_wrap, l_write;
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reg l_wrap, l_write;
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wire b2x_wrap;
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wire b2x_wrap;
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reg [11:0] l_raddr;
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reg [11:0] l_raddr;
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reg [11:0] l_caddr;
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reg [11:0] l_caddr;
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reg l_sdr_dma_last;
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reg l_sdr_dma_last;
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reg bank_prech_page_closed;
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reg bank_prech_page_closed;
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wire tras_ok_internal, tras_ok, activate_bank;
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wire tras_ok_internal, tras_ok, activate_bank;
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wire page_hit, timer0_tc, ld_trp, ld_trcd;
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wire page_hit, timer0_tc, ld_trp, ld_trcd;
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always @ (posedge clk)
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always @ (posedge clk)
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if (~reset_n) begin
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if (~reset_n) begin
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bank_valid <= 1'b0;
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bank_valid <= 1'b0;
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tras_cntr <= 4'b0;
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tras_cntr <= 4'b0;
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timer0 <= 4'b0;
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timer0 <= 4'b0;
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bank_st <= `BANK_IDLE;
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bank_st <= `BANK_IDLE;
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end // if (~reset_n)
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end // if (~reset_n)
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else begin
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else begin
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bank_valid <= (x2b_refresh || bank_prech_page_closed) ? 1'b0 : // force the bank status to be invalid
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bank_valid <= (x2b_refresh || bank_prech_page_closed) ? 1'b0 : // force the bank status to be invalid
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// bank_valid <= (x2b_refresh) ? 1'b0 :
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// bank_valid <= (x2b_refresh) ? 1'b0 :
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(activate_bank) ? 1'b1 : bank_valid;
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(activate_bank) ? 1'b1 : bank_valid;
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tras_cntr <= (activate_bank) ? tras_delay :
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tras_cntr <= (activate_bank) ? tras_delay :
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(~tras_ok_internal) ? tras_cntr - 4'b1 : 4'b0;
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(~tras_ok_internal) ? tras_cntr - 4'b1 : 4'b0;
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timer0 <= (ld_trp) ? trp_delay :
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timer0 <= (ld_trp) ? trp_delay :
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(ld_trcd) ? trcd_delay :
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(ld_trcd) ? trcd_delay :
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(~timer0_tc) ? timer0 - 4'b1 : timer0;
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(~timer0_tc) ? timer0 - 4'b1 : timer0;
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bank_st <= next_bank_st;
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bank_st <= next_bank_st;
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end // else: !if(~reset_n)
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end // else: !if(~reset_n)
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always @ (posedge clk) begin
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always @ (posedge clk) begin
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bank_row <= (activate_bank) ? b2x_addr : bank_row;
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bank_row <= (activate_bank) ? b2x_addr : bank_row;
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if (~reset_n) begin
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if (~reset_n) begin
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l_start <= 1'b0;
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l_start <= 1'b0;
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l_last <= 1'b0;
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l_last <= 1'b0;
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l_id <= 1'b0;
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l_id <= 1'b0;
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l_len <= 1'b0;
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l_len <= 1'b0;
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l_wrap <= 1'b0;
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l_wrap <= 1'b0;
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l_write <= 1'b0;
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l_write <= 1'b0;
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l_raddr <= 1'b0;
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l_raddr <= 1'b0;
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l_caddr <= 1'b0;
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l_caddr <= 1'b0;
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l_sdr_dma_last <= 1'b0;
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l_sdr_dma_last <= 1'b0;
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end
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end
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else begin
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else begin
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if (b2r_ack) begin
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if (b2r_ack) begin
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l_start <= r2b_start;
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l_start <= r2b_start;
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l_last <= r2b_last;
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l_last <= r2b_last;
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l_id <= r2b_req_id;
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l_id <= r2b_req_id;
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l_len <= r2b_len;
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l_len <= r2b_len;
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l_wrap <= r2b_wrap;
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l_wrap <= r2b_wrap;
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l_write <= r2b_write;
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l_write <= r2b_write;
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l_raddr <= r2b_raddr;
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l_raddr <= r2b_raddr;
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l_caddr <= r2b_caddr;
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l_caddr <= r2b_caddr;
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l_sdr_dma_last <= sdr_dma_last;
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l_sdr_dma_last <= sdr_dma_last;
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end // if (b2r_ack)
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end // if (b2r_ack)
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end
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end
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end // always @ (posedge clk)
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end // always @ (posedge clk)
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assign tras_ok_internal = ~|tras_cntr;
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assign tras_ok_internal = ~|tras_cntr;
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assign tras_ok = tras_ok_internal;
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assign tras_ok = tras_ok_internal;
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assign activate_bank = (b2x_cmd == `OP_ACT) & x2b_ack;
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assign activate_bank = (b2x_cmd == `OP_ACT) & x2b_ack;
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assign page_hit = (r2b_raddr == bank_row) ? bank_valid : 1'b0; // its a hit only if bank is valid
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assign page_hit = (r2b_raddr == bank_row) ? bank_valid : 1'b0; // its a hit only if bank is valid
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assign timer0_tc = ~|timer0;
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assign timer0_tc = ~|timer0;
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assign ld_trp = (b2x_cmd == `OP_PRE) ? x2b_ack : 1'b0;
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assign ld_trp = (b2x_cmd == `OP_PRE) ? x2b_ack : 1'b0;
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assign ld_trcd = (b2x_cmd == `OP_ACT) ? x2b_ack : 1'b0;
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assign ld_trcd = (b2x_cmd == `OP_ACT) ? x2b_ack : 1'b0;
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always @ (*) begin
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always @ (*) begin
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bank_prech_page_closed = 1'b0;
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bank_prech_page_closed = 1'b0;
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b2x_req = 1'b0;
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b2x_req = 1'b0;
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b2x_cmd = 2'bx;
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b2x_cmd = 2'bx;
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b2r_ack = 1'b0;
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b2r_ack = 1'b0;
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b2x_addr = 12'bx;
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b2x_addr = 12'bx;
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next_bank_st = bank_st;
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next_bank_st = bank_st;
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case (bank_st)
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case (bank_st)
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`BANK_IDLE : begin
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`BANK_IDLE : begin
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if (~r2b_req) begin
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if (~r2b_req) begin
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bank_prech_page_closed = 1'b0;
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bank_prech_page_closed = 1'b0;
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b2x_req = 1'b0;
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b2x_req = 1'b0;
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b2x_cmd = 2'bx;
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b2x_cmd = 2'bx;
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b2r_ack = 1'b0;
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b2r_ack = 1'b0;
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b2x_addr = 12'bx;
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b2x_addr = 12'bx;
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next_bank_st = `BANK_IDLE;
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next_bank_st = `BANK_IDLE;
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end // if (~r2b_req)
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end // if (~r2b_req)
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else if (page_hit) begin
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else if (page_hit) begin
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b2x_req = (r2b_write) ? x2b_wrok & xfr_ok :
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b2x_req = (r2b_write) ? x2b_wrok & xfr_ok :
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x2b_rdok & xfr_ok;
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x2b_rdok & xfr_ok;
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b2x_cmd = (r2b_write) ? `OP_WR : `OP_RD;
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b2x_cmd = (r2b_write) ? `OP_WR : `OP_RD;
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b2r_ack = 1'b1;
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b2r_ack = 1'b1;
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b2x_addr = r2b_caddr;
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b2x_addr = r2b_caddr;
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next_bank_st = (x2b_ack) ? `BANK_IDLE : `BANK_XFR; // in case of hit, stay here till xfr sm acks
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next_bank_st = (x2b_ack) ? `BANK_IDLE : `BANK_XFR; // in case of hit, stay here till xfr sm acks
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end // if (page_hit)
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end // if (page_hit)
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else begin // page_miss
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else begin // page_miss
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b2x_req = tras_ok_internal & x2b_pre_ok;
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b2x_req = tras_ok_internal & x2b_pre_ok;
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b2x_cmd = `OP_PRE;
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b2x_cmd = `OP_PRE;
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b2r_ack = 1'b1;
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b2r_ack = 1'b1;
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b2x_addr = r2b_raddr & 12'hBFF; // Dont want to pre all banks!
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b2x_addr = r2b_raddr & 12'hBFF; // Dont want to pre all banks!
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next_bank_st = (l_sdr_dma_last) ? `BANK_PRE : (x2b_ack) ? `BANK_ACT : `BANK_PRE; // bank was precharged on l_sdr_dma_last
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next_bank_st = (l_sdr_dma_last) ? `BANK_PRE : (x2b_ack) ? `BANK_ACT : `BANK_PRE; // bank was precharged on l_sdr_dma_last
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end // else: !if(page_hit)
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end // else: !if(page_hit)
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end // case: `BANK_IDLE
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end // case: `BANK_IDLE
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`BANK_PRE : begin
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`BANK_PRE : begin
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b2x_req = tras_ok_internal & x2b_pre_ok;
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b2x_req = tras_ok_internal & x2b_pre_ok;
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b2x_cmd = `OP_PRE;
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b2x_cmd = `OP_PRE;
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b2r_ack = 1'b0;
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b2r_ack = 1'b0;
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b2x_addr = l_raddr & 12'hBFF; // Dont want to pre all banks!
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b2x_addr = l_raddr & 12'hBFF; // Dont want to pre all banks!
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bank_prech_page_closed = 1'b0;
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bank_prech_page_closed = 1'b0;
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next_bank_st = (x2b_ack) ? `BANK_ACT : `BANK_PRE;
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next_bank_st = (x2b_ack) ? `BANK_ACT : `BANK_PRE;
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end // case: `BANK_PRE
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end // case: `BANK_PRE
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`BANK_ACT : begin
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`BANK_ACT : begin
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b2x_req = timer0_tc & x2b_act_ok;
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b2x_req = timer0_tc & x2b_act_ok;
|
b2x_cmd = `OP_ACT;
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b2x_cmd = `OP_ACT;
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b2r_ack = 1'b0;
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b2r_ack = 1'b0;
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b2x_addr = l_raddr;
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b2x_addr = l_raddr;
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bank_prech_page_closed = 1'b0;
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bank_prech_page_closed = 1'b0;
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next_bank_st = (x2b_ack) ? `BANK_XFR : `BANK_ACT;
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next_bank_st = (x2b_ack) ? `BANK_XFR : `BANK_ACT;
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end // case: `BANK_ACT
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end // case: `BANK_ACT
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`BANK_XFR : begin
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`BANK_XFR : begin
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b2x_req = (l_write) ? timer0_tc & x2b_wrok & xfr_ok :
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b2x_req = (l_write) ? timer0_tc & x2b_wrok & xfr_ok :
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timer0_tc & x2b_rdok & xfr_ok;
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timer0_tc & x2b_rdok & xfr_ok;
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b2x_cmd = (l_write) ? `OP_WR : `OP_RD;
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b2x_cmd = (l_write) ? `OP_WR : `OP_RD;
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b2r_ack = 1'b0;
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b2r_ack = 1'b0;
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b2x_addr = l_caddr;
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b2x_addr = l_caddr;
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bank_prech_page_closed = 1'b0;
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bank_prech_page_closed = 1'b0;
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next_bank_st = (x2b_refresh) ? `BANK_ACT :
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next_bank_st = (x2b_refresh) ? `BANK_ACT :
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(x2b_ack & l_sdr_dma_last) ? `BANK_DMA_LAST_PRE :
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(x2b_ack & l_sdr_dma_last) ? `BANK_DMA_LAST_PRE :
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(x2b_ack) ? `BANK_IDLE : `BANK_XFR;
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(x2b_ack) ? `BANK_IDLE : `BANK_XFR;
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end // case: `BANK_XFR
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end // case: `BANK_XFR
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`BANK_DMA_LAST_PRE : begin
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`BANK_DMA_LAST_PRE : begin
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b2x_req = tras_ok_internal & x2b_pre_ok;
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b2x_req = tras_ok_internal & x2b_pre_ok;
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b2x_cmd = `OP_PRE;
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b2x_cmd = `OP_PRE;
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b2r_ack = 1'b0;
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b2r_ack = 1'b0;
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b2x_addr = l_raddr & 12'hBFF; // Dont want to pre all banks!
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b2x_addr = l_raddr & 12'hBFF; // Dont want to pre all banks!
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bank_prech_page_closed = 1'b1;
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bank_prech_page_closed = 1'b1;
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next_bank_st = (x2b_ack) ? `BANK_IDLE : `BANK_DMA_LAST_PRE;
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next_bank_st = (x2b_ack) ? `BANK_IDLE : `BANK_DMA_LAST_PRE;
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end // case: `BANK_DMA_LAST_PRE
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end // case: `BANK_DMA_LAST_PRE
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endcase // case(bank_st)
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endcase // case(bank_st)
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end // always @ (bank_st or ...)
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end // always @ (bank_st or ...)
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assign b2x_start = (bank_st == `BANK_IDLE) ? r2b_start : l_start;
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assign b2x_start = (bank_st == `BANK_IDLE) ? r2b_start : l_start;
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assign b2x_last = (bank_st == `BANK_IDLE) ? r2b_last : l_last;
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assign b2x_last = (bank_st == `BANK_IDLE) ? r2b_last : l_last;
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assign b2x_id = (bank_st == `BANK_IDLE) ? r2b_req_id : l_id;
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assign b2x_id = (bank_st == `BANK_IDLE) ? r2b_req_id : l_id;
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assign b2x_len = (bank_st == `BANK_IDLE) ? r2b_len : l_len;
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assign b2x_len = (bank_st == `BANK_IDLE) ? r2b_len : l_len;
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assign b2x_wrap = (bank_st == `BANK_IDLE) ? r2b_wrap : l_wrap;
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assign b2x_wrap = (bank_st == `BANK_IDLE) ? r2b_wrap : l_wrap;
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endmodule // sdr_bank_fsm
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endmodule // sdr_bank_fsm
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