| Line 91... |
Line 91... |
trcd_delay); // Active to R/W delay
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trcd_delay); // Active to R/W delay
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parameter APP_AW = 30; // Application Address Width
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parameter APP_AW = 30; // Application Address Width
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parameter APP_DW = 32; // Application Data Width
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parameter APP_DW = 32; // Application Data Width
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parameter APP_BW = 4; // Application Byte Width
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parameter APP_BW = 4; // Application Byte Width
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parameter APP_RW = 9; // Application Request Width
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_BW = 2; // SDR Byte Width
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parameter SDR_BW = 2; // SDR Byte Width
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parameter REQ_BW = 12; // Request Width
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input clk, reset_n;
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input clk, reset_n;
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/* Req from bank_ctl */
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/* Req from bank_ctl */
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input r2b_req, r2b_start, r2b_last,
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input r2b_req, r2b_start, r2b_last,
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r2b_write, r2b_wrap;
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r2b_write, r2b_wrap;
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input [`SDR_REQ_ID_W-1:0] r2b_req_id;
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input [`SDR_REQ_ID_W-1:0] r2b_req_id;
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input [11:0] r2b_raddr;
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input [11:0] r2b_raddr;
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input [11:0] r2b_caddr;
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input [11:0] r2b_caddr;
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input [APP_RW-1:0] r2b_len;
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input [REQ_BW-1:0] r2b_len;
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output b2r_ack;
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output b2r_ack;
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input sdr_dma_last;
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input sdr_dma_last;
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/* Req to xfr_ctl */
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/* Req to xfr_ctl */
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output b2x_req, b2x_start, b2x_last,
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output b2x_req, b2x_start, b2x_last,
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tras_ok, b2x_wrap;
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tras_ok, b2x_wrap;
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output [`SDR_REQ_ID_W-1:0] b2x_id;
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output [`SDR_REQ_ID_W-1:0] b2x_id;
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output [11:0] b2x_addr;
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output [11:0] b2x_addr;
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output [APP_RW-1:0] b2x_len;
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output [REQ_BW-1:0] b2x_len;
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output [1:0] b2x_cmd;
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output [1:0] b2x_cmd;
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input x2b_ack;
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input x2b_ack;
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/* Status from xfr_ctl */
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/* Status from xfr_ctl */
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input x2b_refresh, x2b_act_ok, x2b_rdok,
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input x2b_refresh, x2b_act_ok, x2b_rdok,
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| Line 140... |
Line 140... |
reg l_start, l_last;
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reg l_start, l_last;
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reg b2x_req, b2r_ack;
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reg b2x_req, b2r_ack;
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wire [`SDR_REQ_ID_W-1:0] b2x_id;
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wire [`SDR_REQ_ID_W-1:0] b2x_id;
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reg [`SDR_REQ_ID_W-1:0] l_id;
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reg [`SDR_REQ_ID_W-1:0] l_id;
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reg [11:0] b2x_addr;
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reg [11:0] b2x_addr;
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reg [APP_RW-1:0] l_len;
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reg [REQ_BW-1:0] l_len;
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wire [APP_RW-1:0] b2x_len;
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wire [REQ_BW-1:0] b2x_len;
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reg [1:0] b2x_cmd;
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reg [1:0] b2x_cmd;
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reg bank_valid;
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reg bank_valid;
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reg [11:0] bank_row;
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reg [11:0] bank_row;
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reg [3:0] tras_cntr, timer0;
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reg [3:0] tras_cntr, timer0;
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reg l_wrap, l_write;
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reg l_wrap, l_write;
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| Line 168... |
Line 168... |
end // if (~reset_n)
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end // if (~reset_n)
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else begin
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else begin
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bank_valid <= (x2b_refresh || bank_prech_page_closed) ? 1'b0 : // force the bank status to be invalid
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bank_valid <= (x2b_refresh || bank_prech_page_closed) ? 1'b0 : // force the bank status to be invalid
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// bank_valid <= (x2b_refresh) ? 1'b0 :
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(activate_bank) ? 1'b1 : bank_valid;
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(activate_bank) ? 1'b1 : bank_valid;
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tras_cntr <= (activate_bank) ? tras_delay :
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tras_cntr <= (activate_bank) ? tras_delay :
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(~tras_ok_internal) ? tras_cntr - 4'b1 : 4'b0;
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(~tras_ok_internal) ? tras_cntr - 4'b1 : 4'b0;
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