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https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk
[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_bank_fsm.v] - Diff between revs 54 and 55
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Rev 55 |
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Line 88... |
/* SDRAM Timing */
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/* SDRAM Timing */
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tras_delay, // Active to precharge delay
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tras_delay, // Active to precharge delay
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trp_delay, // Precharge to active delay
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trp_delay, // Precharge to active delay
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trcd_delay); // Active to R/W delay
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trcd_delay); // Active to R/W delay
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parameter APP_AW = 30; // Application Address Width
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parameter APP_DW = 32; // Application Data Width
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parameter APP_BW = 4; // Application Byte Width
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_BW = 2; // SDR Byte Width
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parameter SDR_BW = 2; // SDR Byte Width
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input clk, reset_n;
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input clk, reset_n;
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Line 217... |
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end // else: !if(~reset_n)
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end // else: !if(~reset_n)
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always @ (posedge clk) begin
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always @ (posedge clk) begin
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bank_row <= (activate_bank) ? b2x_addr : bank_row;
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bank_row <= (bank_st == `BANK_ACT) ? b2x_addr : bank_row;
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if (~reset_n) begin
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if (~reset_n) begin
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l_start <= 1'b0;
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l_start <= 1'b0;
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l_last <= 1'b0;
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l_last <= 1'b0;
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l_id <= 1'b0;
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l_id <= 1'b0;
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