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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_bank_fsm.v] - Diff between revs 55 and 69

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Rev 55 Rev 69
Line 98... Line 98...
 
 
   /* Req from bank_ctl */
   /* Req from bank_ctl */
   input                        r2b_req, r2b_start, r2b_last,
   input                        r2b_req, r2b_start, r2b_last,
                                r2b_write, r2b_wrap;
                                r2b_write, r2b_wrap;
   input [`SDR_REQ_ID_W-1:0]     r2b_req_id;
   input [`SDR_REQ_ID_W-1:0]     r2b_req_id;
   input [11:0]          r2b_raddr;
   input [12:0]          r2b_raddr;
   input [11:0]          r2b_caddr;
   input [12:0]          r2b_caddr;
   input [`REQ_BW-1:0]   r2b_len;
   input [`REQ_BW-1:0]   r2b_len;
   output                       b2r_ack;
   output                       b2r_ack;
   input                        sdr_dma_last;
   input                        sdr_dma_last;
 
 
   /* Req to xfr_ctl */
   /* Req to xfr_ctl */
   output                       b2x_req, b2x_start, b2x_last,
   output                       b2x_req, b2x_start, b2x_last,
                                tras_ok, b2x_wrap;
                                tras_ok, b2x_wrap;
   output [`SDR_REQ_ID_W-1:0]    b2x_id;
   output [`SDR_REQ_ID_W-1:0]    b2x_id;
   output [11:0]                 b2x_addr;
   output [12:0]                 b2x_addr;
   output [`REQ_BW-1:0]  b2x_len;
   output [`REQ_BW-1:0]  b2x_len;
   output [1:0]          b2x_cmd;
   output [1:0]          b2x_cmd;
   input                        x2b_ack;
   input                        x2b_ack;
 
 
   /* Status from xfr_ctl */
   /* Status from xfr_ctl */
   input                        x2b_refresh, x2b_act_ok, x2b_rdok,
   input                        x2b_refresh, x2b_act_ok, x2b_rdok,
                                x2b_wrok, x2b_pre_ok, xfr_ok;
                                x2b_wrok, x2b_pre_ok, xfr_ok;
 
 
   input [3:0]                   tras_delay, trp_delay, trcd_delay;
   input [3:0]                   tras_delay, trp_delay, trcd_delay;
 
 
   output [11:0]                         bank_row;
   output [12:0]                         bank_row;
 
 
   /****************************************************************************/
   /****************************************************************************/
   // Internal Nets
   // Internal Nets
 
 
   `define BANK_IDLE         3'b000
   `define BANK_IDLE         3'b000
Line 136... Line 136...
   wire                         b2x_start, b2x_last;
   wire                         b2x_start, b2x_last;
   reg                          l_start, l_last;
   reg                          l_start, l_last;
   reg                          b2x_req, b2r_ack;
   reg                          b2x_req, b2r_ack;
   wire [`SDR_REQ_ID_W-1:0]      b2x_id;
   wire [`SDR_REQ_ID_W-1:0]      b2x_id;
   reg [`SDR_REQ_ID_W-1:0]       l_id;
   reg [`SDR_REQ_ID_W-1:0]       l_id;
   reg [11:0]                    b2x_addr;
   reg [12:0]                    b2x_addr;
   reg [`REQ_BW-1:0]     l_len;
   reg [`REQ_BW-1:0]     l_len;
   wire [`REQ_BW-1:0]    b2x_len;
   wire [`REQ_BW-1:0]    b2x_len;
   reg [1:0]                     b2x_cmd_t;
   reg [1:0]                     b2x_cmd_t;
   reg                          bank_valid;
   reg                          bank_valid;
   reg [11:0]                    bank_row;
   reg [12:0]                    bank_row;
   reg [3:0]                     tras_cntr, timer0;
   reg [3:0]                     tras_cntr, timer0;
   reg                          l_wrap, l_write;
   reg                          l_wrap, l_write;
   wire                         b2x_wrap;
   wire                         b2x_wrap;
   reg [11:0]                    l_raddr;
   reg [12:0]                    l_raddr;
   reg [11:0]                    l_caddr;
   reg [12:0]                    l_caddr;
   reg                          l_sdr_dma_last;
   reg                          l_sdr_dma_last;
   reg                          bank_prech_page_closed;
   reg                          bank_prech_page_closed;
 
 
   wire                         tras_ok_internal, tras_ok, activate_bank;
   wire                         tras_ok_internal, tras_ok, activate_bank;
 
 
Line 266... Line 266...
 
 
       bank_prech_page_closed = 1'b0;
       bank_prech_page_closed = 1'b0;
       b2x_req = 1'b0;
       b2x_req = 1'b0;
       b2x_cmd_t = 2'bx;
       b2x_cmd_t = 2'bx;
       b2r_ack = 1'b0;
       b2r_ack = 1'b0;
       b2x_addr = 12'bx;
       b2x_addr = 13'bx;
       next_bank_st = bank_st;
       next_bank_st = bank_st;
 
 
      case (bank_st)
      case (bank_st)
 
 
        `BANK_IDLE : begin
        `BANK_IDLE : begin
Line 292... Line 292...
                     if (~r2b_req) begin
                     if (~r2b_req) begin
                        bank_prech_page_closed = 1'b0;
                        bank_prech_page_closed = 1'b0;
                        b2x_req = 1'b0;
                        b2x_req = 1'b0;
                        b2x_cmd_t = 2'bx;
                        b2x_cmd_t = 2'bx;
                        b2r_ack = 1'b0;
                        b2r_ack = 1'b0;
                        b2x_addr = 12'bx;
                        b2x_addr = 13'bx;
                        next_bank_st = `BANK_IDLE;
                        next_bank_st = `BANK_IDLE;
                     end // if (~r2b_req)
                     end // if (~r2b_req)
                     else if (page_hit) begin
                     else if (page_hit) begin
                        b2x_req = (r2b_write) ? x2b_wrok_t & xfr_ok_t :
                        b2x_req = (r2b_write) ? x2b_wrok_t & xfr_ok_t :
                                               x2b_rdok_t & xfr_ok_t;
                                               x2b_rdok_t & xfr_ok_t;
Line 307... Line 307...
                     end // if (page_hit)
                     end // if (page_hit)
                     else begin  // page_miss
                     else begin  // page_miss
                        b2x_req = tras_ok & x2b_pre_ok_t;
                        b2x_req = tras_ok & x2b_pre_ok_t;
                        b2x_cmd_t = `OP_PRE;
                        b2x_cmd_t = `OP_PRE;
                        b2r_ack = 1'b1;
                        b2r_ack = 1'b1;
                        b2x_addr = r2b_raddr & 12'hBFF;    // Dont want to pre all banks!
                        b2x_addr = r2b_raddr & 13'hBFF;    // Dont want to pre all banks!
                        next_bank_st = (l_sdr_dma_last) ? `BANK_PRE : (x2b_ack) ? `BANK_ACT : `BANK_PRE;  // bank was precharged on l_sdr_dma_last
                        next_bank_st = (l_sdr_dma_last) ? `BANK_PRE : (x2b_ack) ? `BANK_ACT : `BANK_PRE;  // bank was precharged on l_sdr_dma_last
                     end // else: !if(page_hit)
                     end // else: !if(page_hit)
                end
                end
        end // case: `BANK_IDLE
        end // case: `BANK_IDLE
 
 
        `BANK_PRE : begin
        `BANK_PRE : begin
           b2x_req = tras_ok & x2b_pre_ok_t;
           b2x_req = tras_ok & x2b_pre_ok_t;
           b2x_cmd_t = `OP_PRE;
           b2x_cmd_t = `OP_PRE;
           b2r_ack = 1'b0;
           b2r_ack = 1'b0;
           b2x_addr = l_raddr & 12'hBFF;           // Dont want to pre all banks!
           b2x_addr = l_raddr & 13'hBFF;           // Dont want to pre all banks!
           bank_prech_page_closed = 1'b0;
           bank_prech_page_closed = 1'b0;
           next_bank_st = (x2b_ack) ? `BANK_ACT : `BANK_PRE;
           next_bank_st = (x2b_ack) ? `BANK_ACT : `BANK_PRE;
        end // case: `BANK_PRE
        end // case: `BANK_PRE
 
 
        `BANK_ACT : begin
        `BANK_ACT : begin
Line 347... Line 347...
 
 
        `BANK_DMA_LAST_PRE : begin
        `BANK_DMA_LAST_PRE : begin
           b2x_req = tras_ok & x2b_pre_ok_t;
           b2x_req = tras_ok & x2b_pre_ok_t;
           b2x_cmd_t = `OP_PRE;
           b2x_cmd_t = `OP_PRE;
           b2r_ack = 1'b0;
           b2r_ack = 1'b0;
           b2x_addr = l_raddr & 12'hBFF;           // Dont want to pre all banks!
           b2x_addr = l_raddr & 13'hBFF;           // Dont want to pre all banks!
           bank_prech_page_closed = 1'b1;
           bank_prech_page_closed = 1'b1;
           next_bank_st = (x2b_ack) ? `BANK_IDLE : `BANK_DMA_LAST_PRE;
           next_bank_st = (x2b_ack) ? `BANK_IDLE : `BANK_DMA_LAST_PRE;
        end // case: `BANK_DMA_LAST_PRE
        end // case: `BANK_DMA_LAST_PRE
 
 
      endcase // case(bank_st)
      endcase // case(bank_st)

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