/*********************************************************************
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/*********************************************************************
|
|
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SDRAM Controller buswidth converter
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SDRAM Controller buswidth converter
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|
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This file is part of the sdram controller project
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This file is part of the sdram controller project
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http://www.opencores.org/cores/sdr_ctrl/
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http://www.opencores.org/cores/sdr_ctrl/
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|
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Description: SDRAM Controller Buswidth converter
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Description: SDRAM Controller Buswidth converter
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This module does write/read data transalation between
|
This module does write/read data transalation between
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application data to SDRAM bus width
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application data to SDRAM bus width
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To Do:
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To Do:
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nothing
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nothing
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Author(s):
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Author(s):
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- Dinesh Annayya, dinesha@opencores.org
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- Dinesh Annayya, dinesha@opencores.org
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Version : 1.0 - 8th Jan 2012
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Version : 1.0 - 8th Jan 2012
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Copyright (C) 2000 Authors and OPENCORES.ORG
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Copyright (C) 2000 Authors and OPENCORES.ORG
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|
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This source file may be used and distributed without
|
This source file may be used and distributed without
|
restriction provided that this copyright statement is not
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restriction provided that this copyright statement is not
|
removed from the file and that any derivative work contains
|
removed from the file and that any derivative work contains
|
the original copyright notice and the associated disclaimer.
|
the original copyright notice and the associated disclaimer.
|
|
|
This source file is free software; you can redistribute it
|
This source file is free software; you can redistribute it
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and/or modify it under the terms of the GNU Lesser General
|
and/or modify it under the terms of the GNU Lesser General
|
Public License as published by the Free Software Foundation;
|
Public License as published by the Free Software Foundation;
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either version 2.1 of the License, or (at your option) any
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either version 2.1 of the License, or (at your option) any
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later version.
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later version.
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|
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This source is distributed in the hope that it will be
|
This source is distributed in the hope that it will be
|
useful, but WITHOUT ANY WARRANTY; without even the implied
|
useful, but WITHOUT ANY WARRANTY; without even the implied
|
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
PURPOSE. See the GNU Lesser General Public License for more
|
PURPOSE. See the GNU Lesser General Public License for more
|
details.
|
details.
|
|
|
You should have received a copy of the GNU Lesser General
|
You should have received a copy of the GNU Lesser General
|
Public License along with this source; if not, download it
|
Public License along with this source; if not, download it
|
from http://www.opencores.org/lgpl.shtml
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from http://www.opencores.org/lgpl.shtml
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|
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*******************************************************************/
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*******************************************************************/
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|
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`include "sdrc.def"
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`include "sdrc.def"
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module sdrc_bs_convert (
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module sdrc_bs_convert (
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clk,
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clk,
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reset_n,
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reset_n,
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sdr_width,
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sdr_width,
|
|
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app_req_addr,
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app_req_addr,
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app_req_addr_int,
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app_req_addr_int,
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app_req_len,
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app_req_len,
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app_req_len_int,
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app_req_len_int,
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app_req,
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app_sdr_req,
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app_req_int,
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app_sdr_req_int,
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app_req_dma_last,
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app_req_dma_last,
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app_req_dma_last_int,
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app_req_dma_last_int,
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app_req_wr_n,
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app_req_wr_n,
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app_req_ack,
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app_req_ack,
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app_req_ack_int,
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app_req_ack_int,
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app_wr_data,
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app_wr_data,
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app_wr_data_int,
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app_wr_data_int,
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app_wr_en_n,
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app_wr_en_n,
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app_wr_en_n_int,
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app_wr_en_n_int,
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app_wr_next_int,
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app_wr_next_int,
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app_wr_next,
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app_wr_next,
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app_rd_data_int,
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app_rd_data_int,
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app_rd_data,
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app_rd_data,
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app_rd_valid_int,
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app_rd_valid_int,
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app_rd_valid
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app_rd_valid
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);
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);
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parameter APP_AW = 30; // Application Address Width
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parameter APP_AW = 30; // Application Address Width
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parameter APP_DW = 32; // Application Data Width
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parameter APP_DW = 32; // Application Data Width
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parameter APP_BW = 4; // Application Byte Width
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parameter APP_BW = 4; // Application Byte Width
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parameter APP_RW = 9; // Application Request Width
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parameter APP_RW = 9; // Application Request Width
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|
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_BW = 2; // SDR Byte Width
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parameter SDR_BW = 2; // SDR Byte Width
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input clk;
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input clk;
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input reset_n ;
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input reset_n ;
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input sdr_width;
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input sdr_width;
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input [APP_AW-1:0] app_req_addr;
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input [APP_AW-1:0] app_req_addr;
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output [APP_AW:0] app_req_addr_int;
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output [APP_AW:0] app_req_addr_int;
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input [APP_RW-1:0] app_req_len ;
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input [APP_RW-1:0] app_req_len ;
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output [APP_RW-1:0] app_req_len_int;
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output [APP_RW-1:0] app_req_len_int;
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input app_req_wr_n;
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input app_req_wr_n;
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input app_req;
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input app_sdr_req;
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output app_req_int;
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output app_sdr_req_int;
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input app_req_dma_last;
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input app_req_dma_last;
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output app_req_dma_last_int;
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output app_req_dma_last_int;
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input app_req_ack_int;
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input app_req_ack_int;
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output app_req_ack;
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output app_req_ack;
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input [APP_DW-1:0] app_wr_data;
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input [APP_DW-1:0] app_wr_data;
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output [SDR_DW-1:0] app_wr_data_int;
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output [SDR_DW-1:0] app_wr_data_int;
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input [APP_BW-1:0] app_wr_en_n;
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input [APP_BW-1:0] app_wr_en_n;
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output [SDR_BW-1:0] app_wr_en_n_int;
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output [SDR_BW-1:0] app_wr_en_n_int;
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input app_wr_next_int;
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input app_wr_next_int;
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output app_wr_next;
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output app_wr_next;
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input [SDR_DW-1:0] app_rd_data_int;
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input [SDR_DW-1:0] app_rd_data_int;
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output [APP_DW-1:0] app_rd_data;
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output [APP_DW-1:0] app_rd_data;
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input app_rd_valid_int;
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input app_rd_valid_int;
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output app_rd_valid;
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output app_rd_valid;
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reg [APP_AW:0] app_req_addr_int;
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reg [APP_AW:0] app_req_addr_int;
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reg [APP_RW-1:0] app_req_len_int;
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reg [APP_RW-1:0] app_req_len_int;
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reg app_req_dma_last_int;
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reg app_req_dma_last_int;
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reg app_req_int;
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reg app_sdr_req_int;
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reg app_req_ack;
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reg app_req_ack;
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reg [APP_DW-1:0] app_rd_data;
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reg [APP_DW-1:0] app_rd_data;
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reg app_rd_valid;
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reg app_rd_valid;
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reg [SDR_DW-1:0] app_wr_data_int;
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reg [SDR_DW-1:0] app_wr_data_int;
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reg [SDR_BW-1:0] app_wr_en_n_int;
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reg [SDR_BW-1:0] app_wr_en_n_int;
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reg app_wr_next;
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reg app_wr_next;
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|
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reg lcl_rd_valid;
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reg lcl_rd_valid;
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reg lcl_wr_next;
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reg lcl_wr_next;
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reg [15:0] saved_rd_data;
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reg [15:0] saved_rd_data;
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reg save_lower;
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reg save_lower;
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reg upper_word;
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reg upper_word;
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reg write_upper;
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reg write_upper;
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reg [7:0] rd_xfr_count;
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reg [7:0] rd_xfr_count;
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reg [7:0] wr_xfr_count;
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reg [7:0] wr_xfr_count;
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reg [3:0] rd_state,next_rd_state;
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reg [3:0] rd_state,next_rd_state;
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reg [3:0] wr_state,next_wr_state;
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reg [3:0] wr_state,next_wr_state;
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parameter SDR16_IDLE = 0,
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parameter SDR16_IDLE = 0,
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SDR16_RD_LO = 1,
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SDR16_RD_LO = 1,
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SDR16_RD_HI = 2,
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SDR16_RD_HI = 2,
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SDR16_WR_LO = 3,
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SDR16_WR_LO = 3,
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SDR16_WR_HI = 4;
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SDR16_WR_HI = 4;
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wire ok_to_req;
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wire ok_to_req;
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assign ok_to_req = ((wr_state == SDR16_IDLE) && (rd_state == SDR16_IDLE));
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assign ok_to_req = ((wr_state == SDR16_IDLE) && (rd_state == SDR16_IDLE));
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always @(*) begin
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always @(*) begin
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if(!sdr_width) // 32 Bit SDR Mode
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if(!sdr_width) // 32 Bit SDR Mode
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begin
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begin
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app_req_addr_int = {1'b0,app_req_addr};
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app_req_addr_int = {1'b0,app_req_addr};
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app_req_len_int = app_req_len;
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app_req_len_int = app_req_len;
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app_wr_data_int = app_wr_data;
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app_wr_data_int = app_wr_data;
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app_wr_en_n_int = app_wr_en_n;
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app_wr_en_n_int = app_wr_en_n;
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app_req_dma_last_int = app_req_dma_last;
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app_req_dma_last_int = app_req_dma_last;
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app_req_int = app_req;
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app_sdr_req_int = app_sdr_req;
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app_wr_next = app_wr_next_int;
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app_wr_next = app_wr_next_int;
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app_rd_data = app_rd_data_int;
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app_rd_data = app_rd_data_int;
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app_rd_valid = app_rd_valid_int;
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app_rd_valid = app_rd_valid_int;
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app_req_ack = app_req_ack_int;
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app_req_ack = app_req_ack_int;
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end
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end
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else // 16 Bit SDR Mode
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else // 16 Bit SDR Mode
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begin
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begin
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// Changed the address and length to match the 16 bit SDR Mode
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// Changed the address and length to match the 16 bit SDR Mode
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app_req_addr_int = {app_req_addr,1'b0};
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app_req_addr_int = {app_req_addr,1'b0};
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app_req_len_int = {app_req_len,1'b0};
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app_req_len_int = {app_req_len,1'b0};
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app_req_dma_last_int = app_req_dma_last;
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app_req_dma_last_int = app_req_dma_last;
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app_req_int = app_req && ok_to_req;
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app_sdr_req_int = app_sdr_req && ok_to_req;
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app_req_ack = app_req_ack_int;
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app_req_ack = app_req_ack_int;
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app_wr_next = lcl_wr_next;
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app_wr_next = lcl_wr_next;
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app_rd_valid = lcl_rd_valid;
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app_rd_valid = lcl_rd_valid;
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if(write_upper)
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if(write_upper)
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begin
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begin
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app_wr_en_n_int = app_wr_en_n[3:2];
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app_wr_en_n_int = app_wr_en_n[3:2];
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app_wr_data_int = app_wr_data[31:16];
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app_wr_data_int = app_wr_data[31:16];
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end
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end
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else
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else
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begin
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begin
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app_wr_en_n_int = app_wr_en_n[1:0];
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app_wr_en_n_int = app_wr_en_n[1:0];
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app_wr_data_int = app_wr_data[15:0];
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app_wr_data_int = app_wr_data[15:0];
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end
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end
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app_rd_data = {app_rd_data_int[15:0],saved_rd_data};
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app_rd_data = {app_rd_data_int[15:0],saved_rd_data};
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end
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end
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end
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end
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//
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//
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// WRITES
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// WRITES
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//
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//
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always @(*) begin
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always @(*) begin
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|
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lcl_wr_next = 1'b0;
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lcl_wr_next = 1'b0;
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upper_word = 1'b0;
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upper_word = 1'b0;
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next_wr_state = wr_state;
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next_wr_state = wr_state;
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case(wr_state)
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case(wr_state)
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SDR16_IDLE:
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SDR16_IDLE:
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begin
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begin
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if(app_req_ack_int && sdr_width)
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if(app_req_ack_int && sdr_width)
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begin
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begin
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if(~app_req_wr_n)
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if(~app_req_wr_n)
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begin
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begin
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next_wr_state = SDR16_WR_LO;
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next_wr_state = SDR16_WR_LO;
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end
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end
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end
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end
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else
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else
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begin
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begin
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next_wr_state = SDR16_IDLE;
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next_wr_state = SDR16_IDLE;
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end
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end
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end
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end
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SDR16_WR_LO:
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SDR16_WR_LO:
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begin
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begin
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if(app_wr_next)
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if(app_wr_next_int)
|
begin
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begin
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upper_word = 1'b1;
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upper_word = 1'b1;
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next_wr_state = SDR16_WR_HI;
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next_wr_state = SDR16_WR_HI;
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end
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end
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end
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end
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SDR16_WR_HI:
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SDR16_WR_HI:
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begin
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begin
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if(app_wr_next_int)
|
if(app_wr_next_int)
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if(~(|wr_xfr_count))
|
if(~(|wr_xfr_count))
|
begin
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begin
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lcl_wr_next = 1'b1;
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lcl_wr_next = 1'b1;
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next_wr_state = SDR16_IDLE;
|
next_wr_state = SDR16_IDLE;
|
end
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end
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else
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else
|
begin
|
begin
|
lcl_wr_next = 1'b1;
|
lcl_wr_next = 1'b1;
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next_wr_state = SDR16_WR_LO;
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next_wr_state = SDR16_WR_LO;
|
end
|
end
|
end
|
end
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default:
|
default:
|
begin
|
begin
|
next_wr_state = SDR16_IDLE;
|
next_wr_state = SDR16_IDLE;
|
end
|
end
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endcase
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endcase
|
end
|
end
|
//
|
//
|
// READS
|
// READS
|
//
|
//
|
always @(*) begin
|
always @(*) begin
|
|
|
lcl_rd_valid = 1'b0;
|
lcl_rd_valid = 1'b0;
|
save_lower = 1'b0;
|
save_lower = 1'b0;
|
next_rd_state = rd_state;
|
next_rd_state = rd_state;
|
|
|
case(rd_state)
|
case(rd_state)
|
SDR16_IDLE:
|
SDR16_IDLE:
|
begin
|
begin
|
if(app_req_ack_int && sdr_width)
|
if(app_req_ack_int && sdr_width)
|
begin
|
begin
|
if(app_req_wr_n)
|
if(app_req_wr_n)
|
begin
|
begin
|
next_rd_state = SDR16_RD_LO;
|
next_rd_state = SDR16_RD_LO;
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_rd_state = SDR16_IDLE;
|
next_rd_state = SDR16_IDLE;
|
end
|
end
|
end
|
end
|
SDR16_RD_LO:
|
SDR16_RD_LO:
|
begin
|
begin
|
if(app_rd_valid_int)
|
if(app_rd_valid_int)
|
begin
|
begin
|
save_lower = 1'b1;
|
save_lower = 1'b1;
|
next_rd_state = SDR16_RD_HI;
|
next_rd_state = SDR16_RD_HI;
|
end
|
end
|
end
|
end
|
SDR16_RD_HI:
|
SDR16_RD_HI:
|
begin
|
begin
|
if(app_rd_valid_int)
|
if(app_rd_valid_int)
|
if(~(|rd_xfr_count))
|
if(~(|rd_xfr_count))
|
begin
|
begin
|
lcl_rd_valid = 1'b1;
|
lcl_rd_valid = 1'b1;
|
next_rd_state = SDR16_IDLE;
|
next_rd_state = SDR16_IDLE;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
lcl_rd_valid = 1'b1;
|
lcl_rd_valid = 1'b1;
|
next_rd_state = SDR16_RD_LO;
|
next_rd_state = SDR16_RD_LO;
|
end
|
end
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
next_rd_state = SDR16_IDLE;
|
next_rd_state = SDR16_IDLE;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
reg lcl_mc_req_wr_n;
|
reg lcl_mc_req_wr_n;
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
begin
|
begin
|
if(!reset_n)
|
if(!reset_n)
|
begin
|
begin
|
rd_xfr_count <= 8'b0;
|
rd_xfr_count <= 8'b0;
|
wr_xfr_count <= 8'b0;
|
wr_xfr_count <= 8'b0;
|
lcl_mc_req_wr_n <= 1'b1;
|
lcl_mc_req_wr_n <= 1'b1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if(app_req_ack) begin
|
if(app_req_ack) begin
|
wr_xfr_count <= app_req_len - 1'b1;
|
wr_xfr_count <= app_req_len - 1'b1;
|
rd_xfr_count <= app_req_len - 1'b1;
|
rd_xfr_count <= app_req_len - 1'b1;
|
lcl_mc_req_wr_n <= app_req_wr_n;
|
lcl_mc_req_wr_n <= app_req_wr_n;
|
end
|
end
|
else if((lcl_wr_next & !lcl_mc_req_wr_n) || (lcl_rd_valid & lcl_mc_req_wr_n)) begin
|
else if((lcl_wr_next & !lcl_mc_req_wr_n) || (lcl_rd_valid & lcl_mc_req_wr_n)) begin
|
wr_xfr_count <= wr_xfr_count - 1'b1;
|
wr_xfr_count <= wr_xfr_count - 1'b1;
|
rd_xfr_count <= rd_xfr_count - 1'b1;
|
rd_xfr_count <= rd_xfr_count - 1'b1;
|
end
|
end
|
end
|
end
|
end
|
end
|
//
|
//
|
//
|
//
|
always @(posedge clk)
|
always @(posedge clk)
|
begin
|
begin
|
if(!reset_n)
|
if(!reset_n)
|
begin
|
begin
|
rd_state <= SDR16_IDLE;
|
rd_state <= SDR16_IDLE;
|
wr_state <= SDR16_IDLE;
|
wr_state <= SDR16_IDLE;
|
saved_rd_data <= 16'b0;
|
saved_rd_data <= 16'b0;
|
write_upper <= 1'b0;
|
write_upper <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
rd_state <= next_rd_state;
|
rd_state <= next_rd_state;
|
wr_state <= next_wr_state;
|
wr_state <= next_wr_state;
|
if(save_lower)
|
if(save_lower)
|
saved_rd_data <= app_rd_data_int[15:0];
|
saved_rd_data <= app_rd_data_int[15:0];
|
write_upper <= upper_word;
|
write_upper <= upper_word;
|
end
|
end
|
end
|
end
|
|
|
endmodule // sdr_bs_convert
|
endmodule // sdr_bs_convert
|
|
|
