Line 41... |
Line 41... |
0.2 - 2nd Feb 2012
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0.2 - 2nd Feb 2012
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Improved the command pipe structure to accept up-to
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Improved the command pipe structure to accept up-to
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4 command of different bank.
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4 command of different bank.
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0.3 - 7th Feb 2012
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0.3 - 7th Feb 2012
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Bug fix for parameter defination for request length has changed from 9 to 12
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Bug fix for parameter defination for request length has changed from 9 to 12
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0.4 - 26th April 2013
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SDRAM Address Bit is Extended by 12 bit to 13 bit to support higher SDRAM
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Copyright (C) 2000 Authors and OPENCORES.ORG
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Copyright (C) 2000 Authors and OPENCORES.ORG
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This source file may be used and distributed without
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This source file may be used and distributed without
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Line 123... |
Line 125... |
cfg_sdr_trcar_d,
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cfg_sdr_trcar_d,
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cfg_sdr_twr_d,
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cfg_sdr_twr_d,
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cfg_sdr_rfsh,
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cfg_sdr_rfsh,
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cfg_sdr_rfmax);
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cfg_sdr_rfmax);
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parameter APP_AW = 25; // Application Address Width
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parameter APP_AW = 26; // Application Address Width
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parameter APP_DW = 32; // Application Data Width
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parameter APP_DW = 32; // Application Data Width
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parameter APP_BW = 4; // Application Byte Width
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parameter APP_BW = 4; // Application Byte Width
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parameter APP_RW = 9; // Application Request Width
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parameter APP_RW = 9; // Application Request Width
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_DW = 16; // SDR Data Width
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Line 169... |
Line 171... |
output sdr_ras_n ; // SDRAM ras
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output sdr_ras_n ; // SDRAM ras
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output sdr_cas_n ; // SDRAM cas
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output sdr_cas_n ; // SDRAM cas
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output sdr_we_n ; // SDRAM write enable
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output sdr_we_n ; // SDRAM write enable
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output [SDR_BW-1:0] sdr_dqm ; // SDRAM Data Mask
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output [SDR_BW-1:0] sdr_dqm ; // SDRAM Data Mask
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output [1:0] sdr_ba ; // SDRAM Bank Enable
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output [1:0] sdr_ba ; // SDRAM Bank Enable
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output [11:0] sdr_addr ; // SDRAM Address
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output [12:0] sdr_addr ; // SDRAM Address
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input [SDR_DW-1:0] pad_sdr_din ; // SDRA Data Input
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input [SDR_DW-1:0] pad_sdr_din ; // SDRA Data Input
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output [SDR_DW-1:0] sdr_dout ; // SDRAM Data Output
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output [SDR_DW-1:0] sdr_dout ; // SDRAM Data Output
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output [SDR_BW-1:0] sdr_den_n ; // SDRAM Data Output enable
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output [SDR_BW-1:0] sdr_den_n ; // SDRAM Data Output enable
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//------------------------------------------------
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//------------------------------------------------
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Line 184... |
Line 186... |
input [3:0] cfg_sdr_trp_d ; // Precharge to active delay
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input [3:0] cfg_sdr_trp_d ; // Precharge to active delay
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input [3:0] cfg_sdr_trcd_d ; // Active to R/W delay
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input [3:0] cfg_sdr_trcd_d ; // Active to R/W delay
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input cfg_sdr_en ; // Enable SDRAM controller
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input cfg_sdr_en ; // Enable SDRAM controller
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input [1:0] cfg_req_depth ; // Maximum Request accepted by SDRAM controller
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input [1:0] cfg_req_depth ; // Maximum Request accepted by SDRAM controller
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input [APP_RW-1:0] app_req_len ; // Application Burst Request length in 32 bit
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input [APP_RW-1:0] app_req_len ; // Application Burst Request length in 32 bit
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input [11:0] cfg_sdr_mode_reg ;
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input [12:0] cfg_sdr_mode_reg ;
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input [2:0] cfg_sdr_cas ; // SDRAM CAS Latency
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input [2:0] cfg_sdr_cas ; // SDRAM CAS Latency
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input [3:0] cfg_sdr_trcar_d ; // Auto-refresh period
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input [3:0] cfg_sdr_trcar_d ; // Auto-refresh period
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input [3:0] cfg_sdr_twr_d ; // Write recovery delay
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input [3:0] cfg_sdr_twr_d ; // Write recovery delay
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input [`SDR_RFSH_TIMER_W-1 : 0] cfg_sdr_rfsh;
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input [`SDR_RFSH_TIMER_W-1 : 0] cfg_sdr_rfsh;
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input [`SDR_RFSH_ROW_CNT_W -1 : 0] cfg_sdr_rfmax;
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input [`SDR_RFSH_ROW_CNT_W -1 : 0] cfg_sdr_rfmax;
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Line 200... |
// Internal Nets
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// Internal Nets
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// SDR_REQ_GEN
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// SDR_REQ_GEN
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wire [`SDR_REQ_ID_W-1:0]r2b_req_id;
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wire [`SDR_REQ_ID_W-1:0]r2b_req_id;
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wire [1:0] r2b_ba;
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wire [1:0] r2b_ba;
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wire [11:0] r2b_raddr;
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wire [12:0] r2b_raddr;
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wire [11:0] r2b_caddr;
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wire [12:0] r2b_caddr;
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wire [`REQ_BW-1:0] r2b_len;
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wire [`REQ_BW-1:0] r2b_len;
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// SDR BANK CTL
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// SDR BANK CTL
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wire [`SDR_REQ_ID_W-1:0]b2x_id;
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wire [`SDR_REQ_ID_W-1:0]b2x_id;
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wire [1:0] b2x_ba;
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wire [1:0] b2x_ba;
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wire [11:0] b2x_addr;
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wire [12:0] b2x_addr;
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wire [`REQ_BW-1:0] b2x_len;
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wire [`REQ_BW-1:0] b2x_len;
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wire [1:0] b2x_cmd;
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wire [1:0] b2x_cmd;
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// SDR_XFR_CTL
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// SDR_XFR_CTL
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wire [3:0] x2b_pre_ok;
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wire [3:0] x2b_pre_ok;
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wire [`SDR_REQ_ID_W-1:0]xfr_id;
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wire [`SDR_REQ_ID_W-1:0]xfr_id;
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wire [APP_DW-1:0] app_rd_data;
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wire [APP_DW-1:0] app_rd_data;
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wire sdr_cs_n, sdr_cke, sdr_ras_n, sdr_cas_n, sdr_we_n;
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wire sdr_cs_n, sdr_cke, sdr_ras_n, sdr_cas_n, sdr_we_n;
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wire [SDR_BW-1:0] sdr_dqm;
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wire [SDR_BW-1:0] sdr_dqm;
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wire [1:0] sdr_ba;
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wire [1:0] sdr_ba;
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wire [11:0] sdr_addr;
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wire [12:0] sdr_addr;
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wire [SDR_DW-1:0] sdr_dout;
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wire [SDR_DW-1:0] sdr_dout;
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wire [SDR_DW-1:0] sdr_dout_int;
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wire [SDR_DW-1:0] sdr_dout_int;
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wire [SDR_BW-1:0] sdr_den_n;
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wire [SDR_BW-1:0] sdr_den_n;
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wire [SDR_BW-1:0] sdr_den_n_int;
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wire [SDR_BW-1:0] sdr_den_n_int;
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