| Line 259... |
Line 259... |
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assign sdr_den_n = sdr_den_n_int ;
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assign sdr_den_n = sdr_den_n_int ;
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assign sdr_dout = sdr_dout_int ;
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assign sdr_dout = sdr_dout_int ;
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// To meet the timing at read path, read data is registered w.r.t pad_sdram_clock and register back to sdram_clk
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// assumption, pad_sdram_clk is synhronous and delayed clock of sdram_clk.
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// register w.r.t pad sdram clk
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reg [SDR_DW-1:0] pad_sdr_din1;
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reg [SDR_DW-1:0] pad_sdr_din2;
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always@(posedge pad_clk) begin
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pad_sdr_din1 <= pad_sdr_din;
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end
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always@(posedge clk) begin
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pad_sdr_din2 <= pad_sdr_din1;
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end
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/****************************************************************************/
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/****************************************************************************/
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// Instantiate sdr_req_gen
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// Instantiate sdr_req_gen
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// This module takes requests from the app, chops them to burst booundaries
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// This module takes requests from the app, chops them to burst booundaries
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// if wrap=0, decodes the bank and passe the request to bank_ctl
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// if wrap=0, decodes the bank and passe the request to bank_ctl
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| Line 396... |
Line 409... |
.sdr_cas_n (sdr_cas_n ),
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.sdr_cas_n (sdr_cas_n ),
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.sdr_we_n (sdr_we_n ),
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.sdr_we_n (sdr_we_n ),
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.sdr_dqm (sdr_dqm ),
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.sdr_dqm (sdr_dqm ),
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.sdr_ba (sdr_ba ),
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.sdr_ba (sdr_ba ),
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.sdr_addr (sdr_addr ),
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.sdr_addr (sdr_addr ),
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.sdr_din (pad_sdr_din ),
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.sdr_din (pad_sdr_din2 ),
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.sdr_dout (sdr_dout_int ),
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.sdr_dout (sdr_dout_int ),
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.sdr_den_n (sdr_den_n_int ),
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.sdr_den_n (sdr_den_n_int ),
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/* Data Flow to the app */
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/* Data Flow to the app */
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.x2a_rdstart (xfr_rdstart ),
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.x2a_rdstart (xfr_rdstart ),
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