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To Do:
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To Do:
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nothing
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nothing
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Author(s):
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Author(s):
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- Dinesh Annayya, dinesha@opencores.org
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- Dinesh Annayya, dinesha@opencores.org
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Version : 1.0 - 8th Jan 2012
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Version : 0.0 - 8th Jan 2012
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Initial version with 16/32 Bit SDRAM Support
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Initial version with 16/32 Bit SDRAM Support
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: 1.1 - 24th Jan 2012
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: 0.1 - 24th Jan 2012
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8 Bit SDRAM Support is added
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8 Bit SDRAM Support is added
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0.2 - 2nd Feb 2012
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Improved the command pipe structure to accept up-to 4 command of different bank.
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Copyright (C) 2000 Authors and OPENCORES.ORG
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Copyright (C) 2000 Authors and OPENCORES.ORG
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This source file may be used and distributed without
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This source file may be used and distributed without
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Line 251... |
Line 253... |
wire r2b_wrap;
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wire r2b_wrap;
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wire b2r_arb_ok;
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wire b2r_arb_ok;
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wire b2x_wrap;
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wire b2x_wrap;
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wire app_wr_next_int;
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wire app_wr_next_int;
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wire app_rd_valid_int;
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wire app_rd_valid_int;
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wire x2a_rdlast;
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// synopsys translate_off
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// synopsys translate_off
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wire [3:0] sdr_cmd;
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wire [3:0] sdr_cmd;
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assign sdr_cmd = {sdr_cs_n, sdr_ras_n, sdr_cas_n, sdr_we_n};
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assign sdr_cmd = {sdr_cs_n, sdr_ras_n, sdr_cas_n, sdr_we_n};
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// synopsys translate_on
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// synopsys translate_on
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assign sdr_den_n = sdr_den_n_int ;
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assign sdr_den_n = sdr_den_n_int ;
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assign sdr_dout = sdr_dout_int ;
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assign sdr_dout = sdr_dout_int ;
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assign app_last_rd = x2a_rdlast;
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// To meet the timing at read path, read data is registered w.r.t pad_sdram_clock and register back to sdram_clk
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// To meet the timing at read path, read data is registered w.r.t pad_sdram_clock and register back to sdram_clk
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// assumption, pad_sdram_clk is synhronous and delayed clock of sdram_clk.
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// assumption, pad_sdram_clk is synhronous and delayed clock of sdram_clk.
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// register w.r.t pad sdram clk
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// register w.r.t pad sdram clk
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reg [SDR_DW-1:0] pad_sdr_din1;
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reg [SDR_DW-1:0] pad_sdr_din1;
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Line 414... |
Line 419... |
.sdr_ba (sdr_ba ),
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.sdr_ba (sdr_ba ),
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.sdr_addr (sdr_addr ),
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.sdr_addr (sdr_addr ),
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.sdr_din (pad_sdr_din2 ),
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.sdr_din (pad_sdr_din2 ),
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.sdr_dout (sdr_dout_int ),
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.sdr_dout (sdr_dout_int ),
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.sdr_den_n (sdr_den_n_int ),
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.sdr_den_n (sdr_den_n_int ),
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/* Data Flow to the app */
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/* Data Flow to the app */
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.x2a_rdstart (xfr_rdstart ),
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.x2a_rdstart (xfr_rdstart ),
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.x2a_wrstart (xfr_wrstart ),
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.x2a_wrstart (xfr_wrstart ),
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.x2a_id (xfr_id ),
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.x2a_id (xfr_id ),
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.x2a_rdlast (app_last_rd ),
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.x2a_rdlast (x2a_rdlast ),
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.x2a_wrlast (xfr_wrlast ),
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.x2a_wrlast (xfr_wrlast ),
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.app_wrdt (add_wr_data_int ),
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.app_wrdt (add_wr_data_int ),
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.app_wren_n (app_wr_en_n_int ),
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.app_wren_n (app_wr_en_n_int ),
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.x2a_wrnext (app_wr_next_int ),
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.x2a_wrnext (app_wr_next_int ),
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.x2a_rddt (app_rd_data_int ),
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.x2a_rddt (app_rd_data_int ),
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Line 457... |
Line 461... |
sdrc_bs_convert #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_bs_convert (
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sdrc_bs_convert #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_bs_convert (
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.clk (clk ),
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.clk (clk ),
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.reset_n (reset_n ),
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.reset_n (reset_n ),
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.sdr_width (sdr_width ),
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.sdr_width (sdr_width ),
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.app_req_addr (app_req_addr ),
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/* Control Signal from xfr ctrl */
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.x2a_rdstart (xfr_rdstart ),
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.x2a_wrstart (xfr_wrstart ),
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.x2a_rdlast (x2a_rdlast ),
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.x2a_wrlast (xfr_wrlast ),
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.app_rd_data_int (app_rd_data_int ),
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.app_rd_valid_int (app_rd_valid_int ),
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.app_wr_data_int (add_wr_data_int ),
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.app_wr_en_n_int (app_wr_en_n_int ),
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.app_wr_next_int (app_wr_next_int ),
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/* Control Signal from request ctrl */
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.app_req_addr_int (app_req_addr_int ),
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.app_req_addr_int (app_req_addr_int ),
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.app_req_len (app_req_len ),
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.app_req_len_int (app_req_len_int ),
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.app_req_len_int (app_req_len_int ),
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.app_sdr_req (app_req ),
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.app_req_ack_int (app_req_ack_int ),
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.app_sdr_req_int (app_req_int ),
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.app_sdr_req_int (app_req_int ),
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.app_req_dma_last (app_req_dma_last ),
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/* Control Signal from Bank Ctrl */
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.app_req_dma_last_int(app_req_dma_last_int),
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.app_req_dma_last_int(app_req_dma_last_int),
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/* Control Signal from/to to application i/f */
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.app_req_addr (app_req_addr ),
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.app_req_len (app_req_len ),
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.app_sdr_req (app_req ),
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.app_req_dma_last (app_req_dma_last ),
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.app_req_wr_n (app_req_wr_n ),
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.app_req_wr_n (app_req_wr_n ),
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.app_req_ack_int (app_req_ack_int ),
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.app_req_ack (app_req_ack ),
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.app_req_ack (app_req_ack ),
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.app_wr_data (app_wr_data ),
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.app_wr_data (app_wr_data ),
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.app_wr_data_int (add_wr_data_int ),
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.app_wr_en_n (app_wr_en_n ),
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.app_wr_en_n (app_wr_en_n ),
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.app_wr_en_n_int (app_wr_en_n_int ),
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.app_wr_next_int (app_wr_next_int ),
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.app_wr_next (app_wr_next_req ),
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.app_wr_next (app_wr_next_req ),
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.app_rd_data_int (app_rd_data_int ),
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.app_rd_data (app_rd_data ),
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.app_rd_data (app_rd_data ),
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.app_rd_valid_int (app_rd_valid_int ),
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.app_rd_valid (app_rd_valid )
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.app_rd_valid (app_rd_valid )
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);
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);
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endmodule // sdrc_core
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endmodule // sdrc_core
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No newline at end of file
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No newline at end of file
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