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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_core.v] - Diff between revs 47 and 50

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Line 37... Line 37...
  Version  : 0.0 - 8th Jan 2012
  Version  : 0.0 - 8th Jan 2012
                Initial version with 16/32 Bit SDRAM Support
                Initial version with 16/32 Bit SDRAM Support
           : 0.1 - 24th Jan 2012
           : 0.1 - 24th Jan 2012
                 8 Bit SDRAM Support is added
                 8 Bit SDRAM Support is added
             0.2 - 2nd Feb 2012
             0.2 - 2nd Feb 2012
                 Improved the command pipe structure to accept up-to 4 command of different bank.
                   Improved the command pipe structure to accept up-to
 
                   4 command of different bank.
 
             0.3 - 7th Feb 2012
 
                   Bug fix for parameter defination for request length has changed from 9 to 12
 
 
 
 
 Copyright (C) 2000 Authors and OPENCORES.ORG
 Copyright (C) 2000 Authors and OPENCORES.ORG
 
 
 This source file may be used and distributed without
 This source file may be used and distributed without
Line 128... Line 131...
parameter  APP_RW   = 9;   // Application Request Width
parameter  APP_RW   = 9;   // Application Request Width
 
 
parameter  SDR_DW   = 16;  // SDR Data Width 
parameter  SDR_DW   = 16;  // SDR Data Width 
parameter  SDR_BW   = 2;   // SDR Byte Width
parameter  SDR_BW   = 2;   // SDR Byte Width
 
 
 
parameter  REQ_BW   = 12;   //  Request Width
 
 
//-----------------------------------------------
//-----------------------------------------------
// Global Variable
// Global Variable
// ----------------------------------------------
// ----------------------------------------------
input                   clk                 ; // SDRAM Clock 
input                   clk                 ; // SDRAM Clock 
Line 197... Line 201...
// SDR_REQ_GEN
// SDR_REQ_GEN
wire [`SDR_REQ_ID_W-1:0]r2b_req_id;
wire [`SDR_REQ_ID_W-1:0]r2b_req_id;
wire [1:0]               r2b_ba;
wire [1:0]               r2b_ba;
wire [11:0]              r2b_raddr;
wire [11:0]              r2b_raddr;
wire [11:0]              r2b_caddr;
wire [11:0]              r2b_caddr;
wire [APP_RW-1:0]        r2b_len;
wire [REQ_BW-1:0]        r2b_len;
 
 
// SDR BANK CTL
// SDR BANK CTL
wire [`SDR_REQ_ID_W-1:0]b2x_id;
wire [`SDR_REQ_ID_W-1:0]b2x_id;
wire [1:0]               b2x_ba;
wire [1:0]               b2x_ba;
wire [11:0]              b2x_addr;
wire [11:0]              b2x_addr;
wire [APP_RW-1:0]        b2x_len;
wire [REQ_BW-1:0]        b2x_len;
wire [1:0]               b2x_cmd;
wire [1:0]               b2x_cmd;
 
 
// SDR_XFR_CTL
// SDR_XFR_CTL
wire [3:0]               x2b_pre_ok;
wire [3:0]               x2b_pre_ok;
wire [`SDR_REQ_ID_W-1:0]xfr_id;
wire [`SDR_REQ_ID_W-1:0]xfr_id;

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