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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_core.v] - Diff between revs 50 and 51

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Rev 50 Rev 51
Line 131... Line 131...
parameter  APP_RW   = 9;   // Application Request Width
parameter  APP_RW   = 9;   // Application Request Width
 
 
parameter  SDR_DW   = 16;  // SDR Data Width 
parameter  SDR_DW   = 16;  // SDR Data Width 
parameter  SDR_BW   = 2;   // SDR Byte Width
parameter  SDR_BW   = 2;   // SDR Byte Width
 
 
parameter  REQ_BW   = 12;   //  Request Width
// 12 bit subtractor is not feasibile for FPGA, so changed to 8 bits
 
parameter  REQ_BW   = (`TARGET_DESIGN == `FPGA) ? 8 : 12;   //  Request Width
 
 
//-----------------------------------------------
//-----------------------------------------------
// Global Variable
// Global Variable
// ----------------------------------------------
// ----------------------------------------------
input                   clk                 ; // SDRAM Clock 
input                   clk                 ; // SDRAM Clock 

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