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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_core.v] - Diff between revs 51 and 54
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| Rev 51 |
Rev 54 |
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Line 131... |
parameter APP_RW = 9; // Application Request Width
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parameter APP_RW = 9; // Application Request Width
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_BW = 2; // SDR Byte Width
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parameter SDR_BW = 2; // SDR Byte Width
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// 12 bit subtractor is not feasibile for FPGA, so changed to 8 bits
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parameter REQ_BW = (`TARGET_DESIGN == `FPGA) ? 8 : 12; // Request Width
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//-----------------------------------------------
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//-----------------------------------------------
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// Global Variable
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// Global Variable
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// ----------------------------------------------
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// ----------------------------------------------
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input clk ; // SDRAM Clock
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input clk ; // SDRAM Clock
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Line 200... |
// SDR_REQ_GEN
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// SDR_REQ_GEN
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wire [`SDR_REQ_ID_W-1:0]r2b_req_id;
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wire [`SDR_REQ_ID_W-1:0]r2b_req_id;
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wire [1:0] r2b_ba;
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wire [1:0] r2b_ba;
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wire [11:0] r2b_raddr;
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wire [11:0] r2b_raddr;
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wire [11:0] r2b_caddr;
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wire [11:0] r2b_caddr;
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wire [REQ_BW-1:0] r2b_len;
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wire [`REQ_BW-1:0] r2b_len;
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// SDR BANK CTL
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// SDR BANK CTL
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wire [`SDR_REQ_ID_W-1:0]b2x_id;
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wire [`SDR_REQ_ID_W-1:0]b2x_id;
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wire [1:0] b2x_ba;
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wire [1:0] b2x_ba;
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wire [11:0] b2x_addr;
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wire [11:0] b2x_addr;
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wire [REQ_BW-1:0] b2x_len;
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wire [`REQ_BW-1:0] b2x_len;
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wire [1:0] b2x_cmd;
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wire [1:0] b2x_cmd;
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// SDR_XFR_CTL
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// SDR_XFR_CTL
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wire [3:0] x2b_pre_ok;
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wire [3:0] x2b_pre_ok;
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wire [`SDR_REQ_ID_W-1:0]xfr_id;
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wire [`SDR_REQ_ID_W-1:0]xfr_id;
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