| Line 80... |
Line 80... |
req_wrap, // Wrap mode request (xfr_len = 4)
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req_wrap, // Wrap mode request (xfr_len = 4)
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req_wr_n, // 0 => Write request, 1 => read req
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req_wr_n, // 0 => Write request, 1 => read req
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req_ack, // Request has been accepted
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req_ack, // Request has been accepted
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sdr_core_busy_n, // SDRAM Core Busy Indication
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sdr_core_busy_n, // SDRAM Core Busy Indication
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sdr_dev_config, // sdram configuration
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sdr_dev_config, // sdram configuration
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cfg_colbits,
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/* Req to bank_ctl */
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/* Req to bank_ctl */
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r2x_idle,
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r2x_idle,
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r2b_req, // request
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r2b_req, // request
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r2b_req_id, // ID
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r2b_req_id, // ID
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| Line 107... |
Line 108... |
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_BW = 2; // SDR Byte Width
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parameter SDR_BW = 2; // SDR Byte Width
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input clk, reset_n;
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input clk, reset_n;
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input [1:0] cfg_colbits; // 2'b00 - 8 Bit column address, 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
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/* Request from app */
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/* Request from app */
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input req;
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input req;
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input [`SDR_REQ_ID_W-1:0] req_id;
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input [`SDR_REQ_ID_W-1:0] req_id;
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input [APP_AW:0] req_addr;
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input [APP_AW:0] req_addr;
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| Line 163... |
Line 165... |
// All queues end on a 512 byte boundary (actually a 1K boundary). For Q
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// All queues end on a 512 byte boundary (actually a 1K boundary). For Q
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// accesses req_addr_mask is set to LSB of 1 and MSB of 0 to constrain the
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// accesses req_addr_mask is set to LSB of 1 and MSB of 0 to constrain the
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// accesses within the space for a Q. When splitting and calculating the next
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// accesses within the space for a Q. When splitting and calculating the next
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// address only the LSBs are incremented, the MSBs remain = req_addr.
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// address only the LSBs are incremented, the MSBs remain = req_addr.
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//
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//
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assign max_r2b_len = (sdr_width == 1'b0) ? ((sdr_dev_config == `SDR_CONFIG_IS_32M) ? (12'h200 - r2b_caddr) : (12'h100 - r2b_caddr)) :
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assign max_r2b_len = (cfg_colbits == 2'b00) ? (12'h100 - r2b_caddr) :
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(sdr_dev_config == `SDR_CONFIG_IS_8M) ? (12'h100 - r2b_caddr) : (12'h200 - r2b_caddr);
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(cfg_colbits == 2'b01) ? (12'h200 - r2b_caddr) :
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(cfg_colbits == 2'b10) ? (12'h400 - r2b_caddr) : (12'h800 - r2b_caddr);
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assign page_ovflw = ({1'b0, lcl_req_len} > max_r2b_len) ? ~lcl_wrap : 1'b0;
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assign page_ovflw = ({1'b0, lcl_req_len} > max_r2b_len) ? ~lcl_wrap : 1'b0;
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assign r2b_len = (page_ovflw) ? max_r2b_len : lcl_req_len;
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assign r2b_len = (page_ovflw) ? max_r2b_len : lcl_req_len;
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| Line 243... |
Line 246... |
req_st <= next_req_st;
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req_st <= next_req_st;
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end // else: !if(~reset_n)
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end // else: !if(~reset_n)
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//
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//
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// addrs bits for the bank, row and column
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// addrs bits for the bank, row and column
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//
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//
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// SDR_CONFIG_IS_8M 2'b00
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// SDR_CONFIG_IS_16M 2'b01
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// Bank Bits are always - 2 Bits
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// SDR_CONFIG_IS_32M 2'b10
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assign r2b_ba = (cfg_colbits == 2'b00) ? {curr_sdr_addr[9:8]} :
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// SDR_CONFIG_IS_LGCY 2'b11
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(cfg_colbits == 2'b01) ? {curr_sdr_addr[10:9]} :
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//
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(cfg_colbits == 2'b10) ? {curr_sdr_addr[11:10]} : curr_sdr_addr[12:11];
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assign r2b_ba = ({sdr_width,sdr_dev_config} == {1'b0,`SDR_CONFIG_IS_8M}) ? curr_sdr_addr[20:19] :
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({sdr_width,sdr_dev_config} == {1'b0,`SDR_CONFIG_IS_16M}) ? curr_sdr_addr[21:20] :
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/********************
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({sdr_width,sdr_dev_config} == {1'b0,`SDR_CONFIG_IS_32M}) ? curr_sdr_addr[22:21] :
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* Colbits Mapping:
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({sdr_width,sdr_dev_config} == {1'b1,`SDR_CONFIG_IS_8M}) ? curr_sdr_addr[21:20] :
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* 2'b00 - 8 Bit
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({sdr_width,sdr_dev_config} == {1'b1,`SDR_CONFIG_IS_16M}) ? curr_sdr_addr[22:21]:
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* 2'b01 - 16 Bit
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({sdr_width,sdr_dev_config} == {1'b1,`SDR_CONFIG_IS_32M}) ? curr_sdr_addr[23:22] : curr_sdr_addr[9:8];
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* 2'b10 - 10 Bit
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* 2'b11 - 11 Bits
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assign r2b_caddr = ({sdr_width,sdr_dev_config} == {1'b0,`SDR_CONFIG_IS_8M}) ? {4'b0, curr_sdr_addr[7:0]} :
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************************/
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({sdr_width,sdr_dev_config} == {1'b0,`SDR_CONFIG_IS_16M}) ? {4'b0, curr_sdr_addr[7:0]} :
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assign r2b_caddr = (cfg_colbits == 2'b00) ? {4'b0, curr_sdr_addr[7:0]} :
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({sdr_width,sdr_dev_config} == {1'b0,`SDR_CONFIG_IS_32M}) ? {3'b0, curr_sdr_addr[8:0]} :
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(cfg_colbits == 2'b01) ? {3'b0, curr_sdr_addr[8:0]} :
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({sdr_width,sdr_dev_config} == {1'b1,`SDR_CONFIG_IS_8M}) ? {3'b0, curr_sdr_addr[7:0]} :
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(cfg_colbits == 2'b10) ? {2'b0, curr_sdr_addr[9:0]} : {1'b0, curr_sdr_addr[10:0]};
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({sdr_width,sdr_dev_config} == {1'b1,`SDR_CONFIG_IS_16M}) ? {3'b0, curr_sdr_addr[8:0]} :
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({sdr_width,sdr_dev_config} == {1'b1,`SDR_CONFIG_IS_32M}) ? {2'b0, curr_sdr_addr[8:0]} : {4'b0, curr_sdr_addr[7:0]};
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assign r2b_raddr = (cfg_colbits == 2'b00) ? curr_sdr_addr[21:10] :
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(cfg_colbits == 2'b01) ? curr_sdr_addr[22:11] :
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assign r2b_raddr = ({sdr_width,sdr_dev_config} == {1'b0,`SDR_CONFIG_IS_8M}) ? {1'b0, curr_sdr_addr[18:8]} :
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(cfg_colbits == 2'b10) ? curr_sdr_addr[23:12] : curr_sdr_addr[24:13];
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({sdr_width,sdr_dev_config} == {1'b0,`SDR_CONFIG_IS_16M}) ? curr_sdr_addr[19:8] :
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({sdr_width,sdr_dev_config} == {1'b0,`SDR_CONFIG_IS_32M}) ? curr_sdr_addr[20:9] :
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({sdr_width,sdr_dev_config} == {1'b1,`SDR_CONFIG_IS_8M}) ? {1'b0,curr_sdr_addr[19:8]} :
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({sdr_width,sdr_dev_config} == {1'b1,`SDR_CONFIG_IS_16M}) ? curr_sdr_addr[20:9] :
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({sdr_width,sdr_dev_config} == {1'b1,`SDR_CONFIG_IS_32M}) ? curr_sdr_addr[21:9] : {1'b0, curr_sdr_addr[20:10]};
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endmodule // sdr_req_gen
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endmodule // sdr_req_gen
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No newline at end of file
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No newline at end of file
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