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To Do:
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To Do:
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nothing
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nothing
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Author(s):
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Author(s):
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- Dinesh Annayya, dinesha@opencores.org
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- Dinesh Annayya, dinesha@opencores.org
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Version : 1.0 - 8th Jan 2012
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Version : 0.0 - 8th Jan 2012
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0.1 - 5th Feb 2012, column/row/bank address are register to improve the timing issue in FPGA synthesis
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Copyright (C) 2000 Authors and OPENCORES.ORG
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Copyright (C) 2000 Authors and OPENCORES.ORG
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`include "sdrc_define.v"
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`include "sdrc_define.v"
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module sdrc_req_gen (clk,
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module sdrc_req_gen (clk,
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reset_n,
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reset_n,
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cfg_colbits,
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sdr_width,
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/* Request from app */
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/* Request from app */
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req, // Transfer Request
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req, // Transfer Request
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req_id, // ID for this transfer
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req_id, // ID for this transfer
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req_addr, // SDRAM Address
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req_addr, // SDRAM Address
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req_len, // Burst Length (in 32 bit words)
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req_len, // Burst Length (in 32 bit words)
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req_wrap, // Wrap mode request (xfr_len = 4)
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req_wrap, // Wrap mode request (xfr_len = 4)
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req_wr_n, // 0 => Write request, 1 => read req
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req_wr_n, // 0 => Write request, 1 => read req
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req_ack, // Request has been accepted
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req_ack, // Request has been accepted
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sdr_core_busy_n, // SDRAM Core Busy Indication
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cfg_colbits,
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/* Req to bank_ctl */
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/* Req to xfr_ctl */
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r2x_idle,
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r2x_idle,
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/* Req to bank_ctl */
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r2b_req, // request
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r2b_req, // request
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r2b_req_id, // ID
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r2b_req_id, // ID
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r2b_start, // First chunk of burst
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r2b_start, // First chunk of burst
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r2b_last, // Last chunk of burst
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r2b_last, // Last chunk of burst
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r2b_wrap, // Wrap Mode
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r2b_wrap, // Wrap Mode
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r2b_raddr, // row address
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r2b_raddr, // row address
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r2b_caddr, // col address
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r2b_caddr, // col address
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r2b_len, // length
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r2b_len, // length
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r2b_write, // write request
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r2b_write, // write request
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b2r_ack,
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b2r_ack,
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b2r_arb_ok,
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b2r_arb_ok
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sdr_width,
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);
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sdr_init_done);
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parameter APP_AW = 30; // Application Address Width
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parameter APP_AW = 30; // Application Address Width
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parameter APP_DW = 32; // Application Data Width
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parameter APP_DW = 32; // Application Data Width
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parameter APP_BW = 4; // Application Byte Width
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parameter APP_BW = 4; // Application Byte Width
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parameter APP_RW = 9; // Application Request Width
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parameter APP_RW = 9; // Application Request Width
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_BW = 2; // SDR Byte Width
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parameter SDR_BW = 2; // SDR Byte Width
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input clk, reset_n;
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input clk ;
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input reset_n ;
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input [1:0] cfg_colbits; // 2'b00 - 8 Bit column address, 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
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input [1:0] cfg_colbits; // 2'b00 - 8 Bit column address, 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
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/* Request from app */
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/* Request from app */
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input req;
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input req ; // Request
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input [`SDR_REQ_ID_W-1:0] req_id;
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input [`SDR_REQ_ID_W-1:0] req_id ; // Request ID
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input [APP_AW-1:0] req_addr;
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input [APP_AW-1:0] req_addr ; // Request Address
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input [APP_RW-1:0] req_len;
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input [APP_RW-1:0] req_len ; // Request length
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input req_wr_n, req_wrap;
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input req_wr_n ; // 0 -Write, 1 - Read
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output req_ack, sdr_core_busy_n;
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input req_wrap ; // 1 - Wrap the Address on page boundary
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output req_ack ; // Request Ack
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/* Req to bank_ctl */
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/* Req to bank_ctl */
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output r2x_idle, r2b_req, r2b_start, r2b_last,
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output r2x_idle ;
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r2b_write, r2b_wrap;
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output r2b_req ;
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output r2b_start ;
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output r2b_last ;
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output r2b_write ;
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output r2b_wrap ;
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output [`SDR_REQ_ID_W-1:0] r2b_req_id;
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output [`SDR_REQ_ID_W-1:0] r2b_req_id;
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output [1:0] r2b_ba;
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output [1:0] r2b_ba;
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output [11:0] r2b_raddr;
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output [11:0] r2b_raddr;
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output [11:0] r2b_caddr;
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output [11:0] r2b_caddr;
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output [APP_RW-1:0] r2b_len;
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output [APP_RW-1:0] r2b_len;
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input b2r_ack, b2r_arb_ok, sdr_init_done;
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input b2r_ack ;
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input b2r_arb_ok ;
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//
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//
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input [1:0] sdr_width; // 2'b00 - 32 Bit, 2'b01 - 16 Bit, 2'b1x - 8Bit
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input [1:0] sdr_width; // 2'b00 - 32 Bit, 2'b01 - 16 Bit, 2'b1x - 8Bit
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/****************************************************************************/
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/****************************************************************************/
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wire r2b_last, page_ovflw;
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wire r2b_last, page_ovflw;
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wire [APP_RW-1:0] r2b_len, next_req_len;
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wire [APP_RW-1:0] r2b_len, next_req_len;
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wire [APP_RW:0] max_r2b_len;
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wire [APP_RW:0] max_r2b_len;
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wire [1:0] r2b_ba;
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reg [1:0] r2b_ba;
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wire [11:0] r2b_raddr;
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reg [11:0] r2b_raddr;
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wire [11:0] r2b_caddr;
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reg [11:0] r2b_caddr;
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reg [APP_AW-1:0] curr_sdr_addr ;
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reg [APP_AW-1:0] curr_sdr_addr ;
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wire [APP_AW-1:0] next_sdr_addr ;
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wire [APP_AW-1:0] next_sdr_addr ;
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//--------------------------------------------------------------------
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//--------------------------------------------------------------------
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// Generate the internal Adress and Burst length Based on sdram width
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// Generate the internal Adress and Burst length Based on sdram width
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//--------------------------------------------------------------------
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//--------------------------------------------------------------------
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reg [APP_AW:0] req_addr_int;
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reg [APP_AW:0] req_addr_int;
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reg [APP_RW-1:0] req_len_int;
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reg [APP_RW-1:0] req_len_int;
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always @(*) begin
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always @(*) begin
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if(sdr_width == 2'b00) begin // 32 Bit SDR Mode
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if(sdr_width == 2'b00) begin // 32 Bit SDR Mode
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req_addr_int = {1'b0,req_addr};
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req_addr_int = {1'b0,req_addr};
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req_len_int = req_len;
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req_len_int = req_len;
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end else if(sdr_width == 2'b01) begin // 16 Bit SDR Mode
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end else if(sdr_width == 2'b01) begin // 16 Bit SDR Mode
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assign next_req_len = lcl_req_len - r2b_len;
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assign next_req_len = lcl_req_len - r2b_len;
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assign next_sdr_addr = curr_sdr_addr + r2b_len;
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assign next_sdr_addr = curr_sdr_addr + r2b_len;
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assign sdr_core_busy_n = req_idle & b2r_arb_ok & sdr_init_done;
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assign r2b_wrap = lcl_wrap;
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assign r2b_wrap = lcl_wrap;
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assign r2b_last = ~page_ovflw;
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assign r2b_last = ~page_ovflw;
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//
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//
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req_st <= next_req_st;
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req_st <= next_req_st;
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end // else: !if(~reset_n)
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end // else: !if(~reset_n)
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//
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//
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// addrs bits for the bank, row and column
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// addrs bits for the bank, row and column
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//
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//
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// Register row/column/bank to improve fpga timing issue
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wire [APP_AW-1:0] map_address ;
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assign map_address = (req_ack) ? req_addr_int :
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(req_ld) ? next_sdr_addr : curr_sdr_addr;
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always @ (posedge clk) begin
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// Bank Bits are always - 2 Bits
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// Bank Bits are always - 2 Bits
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assign r2b_ba = (cfg_colbits == 2'b00) ? {curr_sdr_addr[9:8]} :
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r2b_ba <= (cfg_colbits == 2'b00) ? {map_address[9:8]} :
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(cfg_colbits == 2'b01) ? {curr_sdr_addr[10:9]} :
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(cfg_colbits == 2'b01) ? {map_address[10:9]} :
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(cfg_colbits == 2'b10) ? {curr_sdr_addr[11:10]} : curr_sdr_addr[12:11];
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(cfg_colbits == 2'b10) ? {map_address[11:10]} : map_address[12:11];
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/********************
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/********************
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* Colbits Mapping:
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* Colbits Mapping:
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* 2'b00 - 8 Bit
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* 2'b00 - 8 Bit
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* 2'b01 - 16 Bit
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* 2'b01 - 16 Bit
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* 2'b10 - 10 Bit
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* 2'b10 - 10 Bit
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* 2'b11 - 11 Bits
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* 2'b11 - 11 Bits
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************************/
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************************/
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assign r2b_caddr = (cfg_colbits == 2'b00) ? {4'b0, curr_sdr_addr[7:0]} :
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r2b_caddr <= (cfg_colbits == 2'b00) ? {4'b0, map_address[7:0]} :
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(cfg_colbits == 2'b01) ? {3'b0, curr_sdr_addr[8:0]} :
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(cfg_colbits == 2'b01) ? {3'b0, map_address[8:0]} :
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(cfg_colbits == 2'b10) ? {2'b0, curr_sdr_addr[9:0]} : {1'b0, curr_sdr_addr[10:0]};
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(cfg_colbits == 2'b10) ? {2'b0, map_address[9:0]} : {1'b0, map_address[10:0]};
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assign r2b_raddr = (cfg_colbits == 2'b00) ? curr_sdr_addr[21:10] :
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r2b_raddr <= (cfg_colbits == 2'b00) ? map_address[21:10] :
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(cfg_colbits == 2'b01) ? curr_sdr_addr[22:11] :
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(cfg_colbits == 2'b01) ? map_address[22:11] :
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(cfg_colbits == 2'b10) ? curr_sdr_addr[23:12] : curr_sdr_addr[24:13];
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(cfg_colbits == 2'b10) ? map_address[23:12] : map_address[24:13];
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end
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endmodule // sdr_req_gen
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endmodule // sdr_req_gen
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No newline at end of file
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No newline at end of file
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