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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_req_gen.v] - Diff between revs 47 and 50

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Rev 47 Rev 50
Line 33... Line 33...
  if the current burst cross the page boundar.
  if the current burst cross the page boundar.
  This module takes requests from the memory controller,
  This module takes requests from the memory controller,
  chops them to page boundaries if wrap=0,
  chops them to page boundaries if wrap=0,
  and passes the request to bank_ctl
  and passes the request to bank_ctl
 
 
 
  Note: With Wrap = 0, each request from Application layer will be splited into two request,
 
        if the current burst cross the page boundary.
 
 
  To Do:
  To Do:
    nothing
    nothing
 
 
  Author(s):
  Author(s):
      - Dinesh Annayya, dinesha@opencores.org
      - Dinesh Annayya, dinesha@opencores.org
Line 110... Line 113...
parameter  APP_RW   = 9;   // Application Request Width
parameter  APP_RW   = 9;   // Application Request Width
 
 
parameter  SDR_DW   = 16;  // SDR Data Width 
parameter  SDR_DW   = 16;  // SDR Data Width 
parameter  SDR_BW   = 2;   // SDR Byte Width
parameter  SDR_BW   = 2;   // SDR Byte Width
 
 
 
parameter  REQ_BW   = 12;   //  Request Width
input                   clk           ;
input                   clk           ;
input                   reset_n       ;
input                   reset_n       ;
input [1:0]             cfg_colbits   ; // 2'b00 - 8 Bit column address, 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
input [1:0]             cfg_colbits   ; // 2'b00 - 8 Bit column address, 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
 
 
/* Request from app */
/* Request from app */
Line 125... Line 129...
input                   req_wrap      ; // 1 - Wrap the Address on page boundary
input                   req_wrap      ; // 1 - Wrap the Address on page boundary
output                  req_ack       ; // Request Ack
output                  req_ack       ; // Request Ack
 
 
/* Req to bank_ctl */
/* Req to bank_ctl */
output                  r2x_idle      ;
output                  r2x_idle      ;
output                  r2b_req       ;
output                  r2b_req       ; // Request
output                  r2b_start     ;
output                  r2b_start     ; // First Junk of the Burst Access
output                  r2b_last      ;
output                  r2b_last      ; // Last Junk of the Burst Access
output                  r2b_write     ;
output                  r2b_write     ; // 1 - Write, 0 - Read
output                  r2b_wrap      ;
output                  r2b_wrap      ; // 1 - Wrap the Address at the page boundary.
output [`SDR_REQ_ID_W-1:0]       r2b_req_id;
output [`SDR_REQ_ID_W-1:0]       r2b_req_id;
output [1:0]             r2b_ba        ;
output [1:0]             r2b_ba        ; // Bank Address
output [11:0]            r2b_raddr     ;
output [11:0]            r2b_raddr     ; // Row Address
output [11:0]            r2b_caddr     ;
output [11:0]            r2b_caddr     ; // Column Address
output [APP_RW-1:0]      r2b_len       ;
output [REQ_BW-1:0]      r2b_len       ; // Burst Length
input                   b2r_ack       ;
input                   b2r_ack       ; // Request Ack
input                   b2r_arb_ok    ;
input                   b2r_arb_ok    ; // Bank controller fifo is not full and ready to accept the command
//
//
input [1:0]              sdr_width; // 2'b00 - 32 Bit, 2'b01 - 16 Bit, 2'b1x - 8Bit
input [1:0]              sdr_width; // 2'b00 - 32 Bit, 2'b01 - 16 Bit, 2'b1x - 8Bit
 
 
 
 
   /****************************************************************************/
   /****************************************************************************/
Line 151... Line 155...
 
 
   reg                  req_st, next_req_st;
   reg                  req_st, next_req_st;
   reg                  r2x_idle, req_ack, r2b_req, r2b_start,
   reg                  r2x_idle, req_ack, r2b_req, r2b_start,
                        r2b_write, req_idle, req_ld, lcl_wrap;
                        r2b_write, req_idle, req_ld, lcl_wrap;
   reg [`SDR_REQ_ID_W-1:0]       r2b_req_id;
   reg [`SDR_REQ_ID_W-1:0]       r2b_req_id;
   reg [APP_RW-1:0]      lcl_req_len;
   reg [REQ_BW-1:0]      lcl_req_len;
 
 
   wire                 r2b_last, page_ovflw;
   wire                 r2b_last, page_ovflw;
   wire [APP_RW-1:0]     r2b_len, next_req_len;
   wire [REQ_BW-1:0]     r2b_len, next_req_len;
   wire [APP_RW:0]       max_r2b_len;
   wire [REQ_BW:0]       max_r2b_len;
 
 
   reg [1:0]             r2b_ba;
   reg [1:0]             r2b_ba;
   reg [11:0]            r2b_raddr;
   reg [11:0]            r2b_raddr;
   reg [11:0]            r2b_caddr;
   reg [11:0]            r2b_caddr;
 
 
Line 209... Line 213...
     //
     //
     // if the wrap = 1, then this block will not modify the request address and length. 
     // if the wrap = 1, then this block will not modify the request address and length. 
     // The wrapping functionality will be handle by the bank control module and 
     // The wrapping functionality will be handle by the bank control module and 
     // column address will rewind back as follows XX -> FF ? 00 ? 1
     // column address will rewind back as follows XX -> FF ? 00 ? 1
     //
     //
 
     // Note: With Wrap = 0, each request from Application layer will be spilited into two request, 
 
     // if the current burst cross the page boundary. 
   assign page_ovflw = ({1'b0, lcl_req_len} > max_r2b_len) ? ~lcl_wrap : 1'b0;
   assign page_ovflw = ({1'b0, lcl_req_len} > max_r2b_len) ? ~lcl_wrap : 1'b0;
 
 
   assign r2b_len = (page_ovflw) ? max_r2b_len : lcl_req_len;
   assign r2b_len = (page_ovflw) ? max_r2b_len : lcl_req_len;
 
 
   assign next_req_len = lcl_req_len - r2b_len;
   assign next_req_len = lcl_req_len - r2b_len;

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