| Line 26... |
Line 26... |
Address[24:13] - Row Address
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Address[24:13] - Row Address
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The SDRAMs are operated in 4 beat burst mode.
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The SDRAMs are operated in 4 beat burst mode.
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If Wrap = 0;
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If Wrap = 0;
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If the current burst cross the page boundary, then this block split the request into two coressponding change in address and request length
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If the current burst cross the page boundary, then this block split the request
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into two coressponding change in address and request length
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if the current burst cross the page boundar.
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if the current burst cross the page boundar.
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This module takes requests from the memory controller,
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This module takes requests from the memory controller,
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chops them to page boundaries if wrap=0,
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chops them to page boundaries if wrap=0,
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and passes the request to bank_ctl
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and passes the request to bank_ctl
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| Line 113... |
Line 114... |
parameter APP_RW = 9; // Application Request Width
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parameter APP_RW = 9; // Application Request Width
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_BW = 2; // SDR Byte Width
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parameter SDR_BW = 2; // SDR Byte Width
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parameter REQ_BW = 12; // Request Width
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// 12 bit subtractor is not feasibile for FPGA, so changed to 8 bits
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parameter REQ_BW = (`TARGET_DESIGN == `FPGA) ? 8 : 12; // Request Width
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input clk ;
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input clk ;
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input reset_n ;
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input reset_n ;
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input [1:0] cfg_colbits ; // 2'b00 - 8 Bit column address, 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
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input [1:0] cfg_colbits ; // 2'b00 - 8 Bit column address, 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
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/* Request from app */
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/* Request from app */
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| Line 159... |
Line 162... |
reg [`SDR_REQ_ID_W-1:0] r2b_req_id;
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reg [`SDR_REQ_ID_W-1:0] r2b_req_id;
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reg [REQ_BW-1:0] lcl_req_len;
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reg [REQ_BW-1:0] lcl_req_len;
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wire r2b_last, page_ovflw;
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wire r2b_last, page_ovflw;
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wire [REQ_BW-1:0] r2b_len, next_req_len;
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wire [REQ_BW-1:0] r2b_len, next_req_len;
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wire [REQ_BW:0] max_r2b_len;
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wire [12:0] max_r2b_len;
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reg [12:0] max_r2b_len_r;
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reg [1:0] r2b_ba;
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reg [1:0] r2b_ba;
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reg [11:0] r2b_raddr;
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reg [11:0] r2b_raddr;
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reg [11:0] r2b_caddr;
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reg [11:0] r2b_caddr;
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| Line 197... |
Line 201... |
// Find the Maximum Burst length allowed from the selected column
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// Find the Maximum Burst length allowed from the selected column
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// address, If the requested burst length is more than the allowed Maximum
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// address, If the requested burst length is more than the allowed Maximum
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// burst length, then we need to handle the bank cross over case and we
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// burst length, then we need to handle the bank cross over case and we
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// need to split the reuest.
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// need to split the reuest.
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//
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//
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assign max_r2b_len = (cfg_colbits == 2'b00) ? (12'h100 - r2b_caddr) :
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assign max_r2b_len = (cfg_colbits == 2'b00) ? (12'h100 - {4'b0, req_addr_int[7:0]}) :
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(cfg_colbits == 2'b01) ? (12'h200 - r2b_caddr) :
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(cfg_colbits == 2'b01) ? (12'h200 - {3'b0, req_addr_int[8:0]}) :
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(cfg_colbits == 2'b10) ? (12'h400 - r2b_caddr) : (12'h800 - r2b_caddr);
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(cfg_colbits == 2'b10) ? (12'h400 - {2'b0, req_addr_int[9:0]}) : (12'h800 - {1'b0, req_addr_int[10:0]});
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// If the wrap = 0 and current application burst length is crossing the page boundary,
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// If the wrap = 0 and current application burst length is crossing the page boundary,
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// then request will be split into two with corresponding change in request address and request length.
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// then request will be split into two with corresponding change in request address and request length.
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//
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//
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| Line 215... |
Line 219... |
// The wrapping functionality will be handle by the bank control module and
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// The wrapping functionality will be handle by the bank control module and
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// column address will rewind back as follows XX -> FF ? 00 ? 1
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// column address will rewind back as follows XX -> FF ? 00 ? 1
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//
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//
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// Note: With Wrap = 0, each request from Application layer will be spilited into two request,
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// Note: With Wrap = 0, each request from Application layer will be spilited into two request,
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// if the current burst cross the page boundary.
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// if the current burst cross the page boundary.
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assign page_ovflw = ({1'b0, lcl_req_len} > max_r2b_len) ? ~lcl_wrap : 1'b0;
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assign page_ovflw = ({1'b0, lcl_req_len} > max_r2b_len_r) ? ~lcl_wrap : 1'b0;
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assign r2b_len = (page_ovflw) ? max_r2b_len : lcl_req_len;
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assign r2b_len = (page_ovflw) ? max_r2b_len_r : lcl_req_len;
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assign next_req_len = lcl_req_len - r2b_len;
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assign next_req_len = lcl_req_len - r2b_len;
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assign next_sdr_addr = curr_sdr_addr + r2b_len;
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assign next_sdr_addr = curr_sdr_addr + r2b_len;
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| Line 232... |
Line 236... |
//
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//
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//
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//
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//
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//
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always @ (posedge clk) begin
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always @ (posedge clk) begin
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max_r2b_len_r <= max_r2b_len;
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r2b_start <= (req_ack) ? 1'b1 :
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r2b_start <= (req_ack) ? 1'b1 :
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(b2r_ack) ? 1'b0 : r2b_start;
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(b2r_ack) ? 1'b0 : r2b_start;
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r2b_write <= (req_ack) ? ~req_wr_n : r2b_write;
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r2b_write <= (req_ack) ? ~req_wr_n : r2b_write;
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