/*********************************************************************
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/*********************************************************************
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SDRAM Controller Request Generation
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SDRAM Controller Request Generation
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This file is part of the sdram controller project
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This file is part of the sdram controller project
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http://www.opencores.org/cores/sdr_ctrl/
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http://www.opencores.org/cores/sdr_ctrl/
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Description: SDRAM Controller Reguest Generation
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Description: SDRAM Controller Reguest Generation
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Address Generation Based on cfg_colbits
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Address Generation Based on cfg_colbits
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cfg_colbits= 2'b00
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cfg_colbits= 2'b00
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Address[7:0] - Column Address
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Address[7:0] - Column Address
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Address[9:8] - Bank Address
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Address[9:8] - Bank Address
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Address[21:10] - Row Address
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Address[21:10] - Row Address
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cfg_colbits= 2'b01
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cfg_colbits= 2'b01
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Address[8:0] - Column Address
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Address[8:0] - Column Address
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Address[10:9] - Bank Address
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Address[10:9] - Bank Address
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Address[22:11] - Row Address
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Address[22:11] - Row Address
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cfg_colbits= 2'b10
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cfg_colbits= 2'b10
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Address[9:0] - Column Address
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Address[9:0] - Column Address
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Address[11:10] - Bank Address
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Address[11:10] - Bank Address
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Address[23:12] - Row Address
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Address[23:12] - Row Address
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cfg_colbits= 2'b11
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cfg_colbits= 2'b11
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Address[10:0] - Column Address
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Address[10:0] - Column Address
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Address[12:11] - Bank Address
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Address[12:11] - Bank Address
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Address[24:13] - Row Address
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Address[24:13] - Row Address
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The SDRAMs are operated in 4 beat burst mode.
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The SDRAMs are operated in 4 beat burst mode.
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If Wrap = 0;
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If Wrap = 0;
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If the current burst cross the page boundary, then this block split the request into two coressponding change in address and request length
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If the current burst cross the page boundary, then this block split the request
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into two coressponding change in address and request length
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if the current burst cross the page boundar.
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if the current burst cross the page boundar.
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This module takes requests from the memory controller,
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This module takes requests from the memory controller,
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chops them to page boundaries if wrap=0,
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chops them to page boundaries if wrap=0,
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and passes the request to bank_ctl
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and passes the request to bank_ctl
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Note: With Wrap = 0, each request from Application layer will be splited into two request,
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Note: With Wrap = 0, each request from Application layer will be splited into two request,
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if the current burst cross the page boundary.
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if the current burst cross the page boundary.
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To Do:
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To Do:
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nothing
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nothing
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Author(s):
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Author(s):
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- Dinesh Annayya, dinesha@opencores.org
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- Dinesh Annayya, dinesha@opencores.org
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Version : 0.0 - 8th Jan 2012
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Version : 0.0 - 8th Jan 2012
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0.1 - 5th Feb 2012, column/row/bank address are register to improve the timing issue in FPGA synthesis
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0.1 - 5th Feb 2012, column/row/bank address are register to improve the timing issue in FPGA synthesis
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Copyright (C) 2000 Authors and OPENCORES.ORG
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Copyright (C) 2000 Authors and OPENCORES.ORG
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This source file may be used and distributed without
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This source file may be used and distributed without
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restriction provided that this copyright statement is not
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restriction provided that this copyright statement is not
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removed from the file and that any derivative work contains
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removed from the file and that any derivative work contains
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the original copyright notice and the associated disclaimer.
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the original copyright notice and the associated disclaimer.
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This source file is free software; you can redistribute it
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This source file is free software; you can redistribute it
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and/or modify it under the terms of the GNU Lesser General
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and/or modify it under the terms of the GNU Lesser General
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Public License as published by the Free Software Foundation;
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Public License as published by the Free Software Foundation;
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either version 2.1 of the License, or (at your option) any
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either version 2.1 of the License, or (at your option) any
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later version.
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later version.
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This source is distributed in the hope that it will be
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This source is distributed in the hope that it will be
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useful, but WITHOUT ANY WARRANTY; without even the implied
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useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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PURPOSE. See the GNU Lesser General Public License for more
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PURPOSE. See the GNU Lesser General Public License for more
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details.
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details.
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You should have received a copy of the GNU Lesser General
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You should have received a copy of the GNU Lesser General
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Public License along with this source; if not, download it
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Public License along with this source; if not, download it
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from http://www.opencores.org/lgpl.shtml
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from http://www.opencores.org/lgpl.shtml
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*******************************************************************/
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*******************************************************************/
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`include "sdrc_define.v"
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`include "sdrc_define.v"
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module sdrc_req_gen (clk,
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module sdrc_req_gen (clk,
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reset_n,
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reset_n,
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cfg_colbits,
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cfg_colbits,
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sdr_width,
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sdr_width,
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/* Request from app */
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/* Request from app */
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req, // Transfer Request
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req, // Transfer Request
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req_id, // ID for this transfer
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req_id, // ID for this transfer
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req_addr, // SDRAM Address
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req_addr, // SDRAM Address
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req_len, // Burst Length (in 32 bit words)
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req_len, // Burst Length (in 32 bit words)
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req_wrap, // Wrap mode request (xfr_len = 4)
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req_wrap, // Wrap mode request (xfr_len = 4)
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req_wr_n, // 0 => Write request, 1 => read req
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req_wr_n, // 0 => Write request, 1 => read req
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req_ack, // Request has been accepted
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req_ack, // Request has been accepted
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/* Req to xfr_ctl */
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/* Req to xfr_ctl */
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r2x_idle,
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r2x_idle,
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/* Req to bank_ctl */
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/* Req to bank_ctl */
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r2b_req, // request
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r2b_req, // request
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r2b_req_id, // ID
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r2b_req_id, // ID
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r2b_start, // First chunk of burst
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r2b_start, // First chunk of burst
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r2b_last, // Last chunk of burst
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r2b_last, // Last chunk of burst
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r2b_wrap, // Wrap Mode
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r2b_wrap, // Wrap Mode
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r2b_ba, // bank address
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r2b_ba, // bank address
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r2b_raddr, // row address
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r2b_raddr, // row address
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r2b_caddr, // col address
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r2b_caddr, // col address
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r2b_len, // length
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r2b_len, // length
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r2b_write, // write request
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r2b_write, // write request
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b2r_ack,
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b2r_ack,
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b2r_arb_ok
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b2r_arb_ok
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);
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);
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parameter APP_AW = 30; // Application Address Width
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parameter APP_AW = 30; // Application Address Width
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parameter APP_DW = 32; // Application Data Width
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parameter APP_DW = 32; // Application Data Width
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parameter APP_BW = 4; // Application Byte Width
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parameter APP_BW = 4; // Application Byte Width
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parameter APP_RW = 9; // Application Request Width
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parameter APP_RW = 9; // Application Request Width
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_BW = 2; // SDR Byte Width
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parameter SDR_BW = 2; // SDR Byte Width
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parameter REQ_BW = 12; // Request Width
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// 12 bit subtractor is not feasibile for FPGA, so changed to 8 bits
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parameter REQ_BW = (`TARGET_DESIGN == `FPGA) ? 8 : 12; // Request Width
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input clk ;
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input clk ;
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input reset_n ;
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input reset_n ;
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input [1:0] cfg_colbits ; // 2'b00 - 8 Bit column address, 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
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input [1:0] cfg_colbits ; // 2'b00 - 8 Bit column address, 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
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/* Request from app */
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/* Request from app */
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input req ; // Request
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input req ; // Request
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input [`SDR_REQ_ID_W-1:0] req_id ; // Request ID
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input [`SDR_REQ_ID_W-1:0] req_id ; // Request ID
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input [APP_AW-1:0] req_addr ; // Request Address
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input [APP_AW-1:0] req_addr ; // Request Address
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input [APP_RW-1:0] req_len ; // Request length
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input [APP_RW-1:0] req_len ; // Request length
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input req_wr_n ; // 0 -Write, 1 - Read
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input req_wr_n ; // 0 -Write, 1 - Read
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input req_wrap ; // 1 - Wrap the Address on page boundary
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input req_wrap ; // 1 - Wrap the Address on page boundary
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output req_ack ; // Request Ack
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output req_ack ; // Request Ack
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/* Req to bank_ctl */
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/* Req to bank_ctl */
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output r2x_idle ;
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output r2x_idle ;
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output r2b_req ; // Request
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output r2b_req ; // Request
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output r2b_start ; // First Junk of the Burst Access
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output r2b_start ; // First Junk of the Burst Access
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output r2b_last ; // Last Junk of the Burst Access
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output r2b_last ; // Last Junk of the Burst Access
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output r2b_write ; // 1 - Write, 0 - Read
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output r2b_write ; // 1 - Write, 0 - Read
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output r2b_wrap ; // 1 - Wrap the Address at the page boundary.
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output r2b_wrap ; // 1 - Wrap the Address at the page boundary.
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output [`SDR_REQ_ID_W-1:0] r2b_req_id;
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output [`SDR_REQ_ID_W-1:0] r2b_req_id;
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output [1:0] r2b_ba ; // Bank Address
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output [1:0] r2b_ba ; // Bank Address
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output [11:0] r2b_raddr ; // Row Address
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output [11:0] r2b_raddr ; // Row Address
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output [11:0] r2b_caddr ; // Column Address
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output [11:0] r2b_caddr ; // Column Address
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output [REQ_BW-1:0] r2b_len ; // Burst Length
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output [REQ_BW-1:0] r2b_len ; // Burst Length
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input b2r_ack ; // Request Ack
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input b2r_ack ; // Request Ack
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input b2r_arb_ok ; // Bank controller fifo is not full and ready to accept the command
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input b2r_arb_ok ; // Bank controller fifo is not full and ready to accept the command
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//
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//
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input [1:0] sdr_width; // 2'b00 - 32 Bit, 2'b01 - 16 Bit, 2'b1x - 8Bit
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input [1:0] sdr_width; // 2'b00 - 32 Bit, 2'b01 - 16 Bit, 2'b1x - 8Bit
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/****************************************************************************/
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/****************************************************************************/
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// Internal Nets
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// Internal Nets
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`define REQ_IDLE 1'b0
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`define REQ_IDLE 1'b0
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`define REQ_ACTIVE 1'b1
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`define REQ_ACTIVE 1'b1
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reg req_st, next_req_st;
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reg req_st, next_req_st;
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reg r2x_idle, req_ack, r2b_req, r2b_start,
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reg r2x_idle, req_ack, r2b_req, r2b_start,
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r2b_write, req_idle, req_ld, lcl_wrap;
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r2b_write, req_idle, req_ld, lcl_wrap;
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reg [`SDR_REQ_ID_W-1:0] r2b_req_id;
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reg [`SDR_REQ_ID_W-1:0] r2b_req_id;
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reg [REQ_BW-1:0] lcl_req_len;
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reg [REQ_BW-1:0] lcl_req_len;
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wire r2b_last, page_ovflw;
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wire r2b_last, page_ovflw;
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wire [REQ_BW-1:0] r2b_len, next_req_len;
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wire [REQ_BW-1:0] r2b_len, next_req_len;
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wire [REQ_BW:0] max_r2b_len;
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wire [12:0] max_r2b_len;
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reg [12:0] max_r2b_len_r;
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reg [1:0] r2b_ba;
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reg [1:0] r2b_ba;
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reg [11:0] r2b_raddr;
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reg [11:0] r2b_raddr;
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reg [11:0] r2b_caddr;
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reg [11:0] r2b_caddr;
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reg [APP_AW-1:0] curr_sdr_addr ;
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reg [APP_AW-1:0] curr_sdr_addr ;
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wire [APP_AW-1:0] next_sdr_addr ;
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wire [APP_AW-1:0] next_sdr_addr ;
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//--------------------------------------------------------------------
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//--------------------------------------------------------------------
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// Generate the internal Adress and Burst length Based on sdram width
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// Generate the internal Adress and Burst length Based on sdram width
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//--------------------------------------------------------------------
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//--------------------------------------------------------------------
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reg [APP_AW:0] req_addr_int;
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reg [APP_AW:0] req_addr_int;
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reg [APP_RW-1:0] req_len_int;
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reg [APP_RW-1:0] req_len_int;
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always @(*) begin
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always @(*) begin
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if(sdr_width == 2'b00) begin // 32 Bit SDR Mode
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if(sdr_width == 2'b00) begin // 32 Bit SDR Mode
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req_addr_int = {1'b0,req_addr};
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req_addr_int = {1'b0,req_addr};
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req_len_int = req_len;
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req_len_int = req_len;
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end else if(sdr_width == 2'b01) begin // 16 Bit SDR Mode
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end else if(sdr_width == 2'b01) begin // 16 Bit SDR Mode
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// Changed the address and length to match the 16 bit SDR Mode
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// Changed the address and length to match the 16 bit SDR Mode
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req_addr_int = {req_addr,1'b0};
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req_addr_int = {req_addr,1'b0};
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req_len_int = {req_len,1'b0};
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req_len_int = {req_len,1'b0};
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end else begin // 8 Bit SDR Mode
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end else begin // 8 Bit SDR Mode
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// Changed the address and length to match the 16 bit SDR Mode
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// Changed the address and length to match the 16 bit SDR Mode
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req_addr_int = {req_addr,2'b0};
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req_addr_int = {req_addr,2'b0};
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req_len_int = {req_len,2'b0};
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req_len_int = {req_len,2'b0};
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end
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end
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end
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end
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//
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//
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// Identify the page over flow.
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// Identify the page over flow.
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// Find the Maximum Burst length allowed from the selected column
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// Find the Maximum Burst length allowed from the selected column
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// address, If the requested burst length is more than the allowed Maximum
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// address, If the requested burst length is more than the allowed Maximum
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// burst length, then we need to handle the bank cross over case and we
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// burst length, then we need to handle the bank cross over case and we
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// need to split the reuest.
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// need to split the reuest.
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//
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//
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assign max_r2b_len = (cfg_colbits == 2'b00) ? (12'h100 - r2b_caddr) :
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assign max_r2b_len = (cfg_colbits == 2'b00) ? (12'h100 - {4'b0, req_addr_int[7:0]}) :
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(cfg_colbits == 2'b01) ? (12'h200 - r2b_caddr) :
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(cfg_colbits == 2'b01) ? (12'h200 - {3'b0, req_addr_int[8:0]}) :
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(cfg_colbits == 2'b10) ? (12'h400 - r2b_caddr) : (12'h800 - r2b_caddr);
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(cfg_colbits == 2'b10) ? (12'h400 - {2'b0, req_addr_int[9:0]}) : (12'h800 - {1'b0, req_addr_int[10:0]});
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// If the wrap = 0 and current application burst length is crossing the page boundary,
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// If the wrap = 0 and current application burst length is crossing the page boundary,
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// then request will be split into two with corresponding change in request address and request length.
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// then request will be split into two with corresponding change in request address and request length.
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//
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//
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// If the wrap = 0 and current burst length is not crossing the page boundary,
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// If the wrap = 0 and current burst length is not crossing the page boundary,
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// then request from application layer will be transparently passed on the bank control block.
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// then request from application layer will be transparently passed on the bank control block.
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//
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//
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// if the wrap = 1, then this block will not modify the request address and length.
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// if the wrap = 1, then this block will not modify the request address and length.
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// The wrapping functionality will be handle by the bank control module and
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// The wrapping functionality will be handle by the bank control module and
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// column address will rewind back as follows XX -> FF ? 00 ? 1
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// column address will rewind back as follows XX -> FF ? 00 ? 1
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//
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//
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// Note: With Wrap = 0, each request from Application layer will be spilited into two request,
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// Note: With Wrap = 0, each request from Application layer will be spilited into two request,
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// if the current burst cross the page boundary.
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// if the current burst cross the page boundary.
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assign page_ovflw = ({1'b0, lcl_req_len} > max_r2b_len) ? ~lcl_wrap : 1'b0;
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assign page_ovflw = ({1'b0, lcl_req_len} > max_r2b_len_r) ? ~lcl_wrap : 1'b0;
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assign r2b_len = (page_ovflw) ? max_r2b_len : lcl_req_len;
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assign r2b_len = (page_ovflw) ? max_r2b_len_r : lcl_req_len;
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assign next_req_len = lcl_req_len - r2b_len;
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assign next_req_len = lcl_req_len - r2b_len;
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assign next_sdr_addr = curr_sdr_addr + r2b_len;
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assign next_sdr_addr = curr_sdr_addr + r2b_len;
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assign r2b_wrap = lcl_wrap;
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assign r2b_wrap = lcl_wrap;
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assign r2b_last = ~page_ovflw;
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assign r2b_last = ~page_ovflw;
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//
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//
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//
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//
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//
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//
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always @ (posedge clk) begin
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always @ (posedge clk) begin
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max_r2b_len_r <= max_r2b_len;
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r2b_start <= (req_ack) ? 1'b1 :
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r2b_start <= (req_ack) ? 1'b1 :
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(b2r_ack) ? 1'b0 : r2b_start;
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(b2r_ack) ? 1'b0 : r2b_start;
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r2b_write <= (req_ack) ? ~req_wr_n : r2b_write;
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r2b_write <= (req_ack) ? ~req_wr_n : r2b_write;
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r2b_req_id <= (req_ack) ? req_id : r2b_req_id;
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r2b_req_id <= (req_ack) ? req_id : r2b_req_id;
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lcl_wrap <= (req_ack) ? req_wrap : lcl_wrap;
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lcl_wrap <= (req_ack) ? req_wrap : lcl_wrap;
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lcl_req_len <= (req_ack) ? req_len_int :
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lcl_req_len <= (req_ack) ? req_len_int :
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(req_ld) ? next_req_len : lcl_req_len;
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(req_ld) ? next_req_len : lcl_req_len;
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curr_sdr_addr <= (req_ack) ? req_addr_int :
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curr_sdr_addr <= (req_ack) ? req_addr_int :
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(req_ld) ? next_sdr_addr : curr_sdr_addr;
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(req_ld) ? next_sdr_addr : curr_sdr_addr;
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end // always @ (posedge clk)
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end // always @ (posedge clk)
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always @ (*) begin
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always @ (*) begin
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case (req_st) // synopsys full_case parallel_case
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case (req_st) // synopsys full_case parallel_case
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`REQ_IDLE : begin
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`REQ_IDLE : begin
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r2x_idle = ~req;
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r2x_idle = ~req;
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req_idle = 1'b1;
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req_idle = 1'b1;
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req_ack = req & b2r_arb_ok;
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req_ack = req & b2r_arb_ok;
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req_ld = 1'b0;
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req_ld = 1'b0;
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r2b_req = 1'b0;
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r2b_req = 1'b0;
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next_req_st = (req & b2r_arb_ok) ? `REQ_ACTIVE : `REQ_IDLE;
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next_req_st = (req & b2r_arb_ok) ? `REQ_ACTIVE : `REQ_IDLE;
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end // case: `REQ_IDLE
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end // case: `REQ_IDLE
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`REQ_ACTIVE : begin
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`REQ_ACTIVE : begin
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r2x_idle = 1'b0;
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r2x_idle = 1'b0;
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req_idle = 1'b0;
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req_idle = 1'b0;
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req_ack = 1'b0;
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req_ack = 1'b0;
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req_ld = b2r_ack;
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req_ld = b2r_ack;
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r2b_req = 1'b1; // req_gen to bank_req
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r2b_req = 1'b1; // req_gen to bank_req
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next_req_st = (b2r_ack & r2b_last) ? `REQ_IDLE : `REQ_ACTIVE;
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next_req_st = (b2r_ack & r2b_last) ? `REQ_IDLE : `REQ_ACTIVE;
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end // case: `REQ_ACTIVE
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end // case: `REQ_ACTIVE
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endcase // case(req_st)
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endcase // case(req_st)
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end // always @ (req_st or ....)
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end // always @ (req_st or ....)
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always @ (posedge clk)
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always @ (posedge clk)
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if (~reset_n) begin
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if (~reset_n) begin
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req_st <= `REQ_IDLE;
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req_st <= `REQ_IDLE;
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end // if (~reset_n)
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end // if (~reset_n)
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else begin
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else begin
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req_st <= next_req_st;
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req_st <= next_req_st;
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end // else: !if(~reset_n)
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end // else: !if(~reset_n)
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//
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//
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// addrs bits for the bank, row and column
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// addrs bits for the bank, row and column
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//
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//
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// Register row/column/bank to improve fpga timing issue
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// Register row/column/bank to improve fpga timing issue
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wire [APP_AW-1:0] map_address ;
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wire [APP_AW-1:0] map_address ;
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|
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assign map_address = (req_ack) ? req_addr_int :
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assign map_address = (req_ack) ? req_addr_int :
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(req_ld) ? next_sdr_addr : curr_sdr_addr;
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(req_ld) ? next_sdr_addr : curr_sdr_addr;
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|
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always @ (posedge clk) begin
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always @ (posedge clk) begin
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// Bank Bits are always - 2 Bits
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// Bank Bits are always - 2 Bits
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r2b_ba <= (cfg_colbits == 2'b00) ? {map_address[9:8]} :
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r2b_ba <= (cfg_colbits == 2'b00) ? {map_address[9:8]} :
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(cfg_colbits == 2'b01) ? {map_address[10:9]} :
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(cfg_colbits == 2'b01) ? {map_address[10:9]} :
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(cfg_colbits == 2'b10) ? {map_address[11:10]} : map_address[12:11];
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(cfg_colbits == 2'b10) ? {map_address[11:10]} : map_address[12:11];
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|
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/********************
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/********************
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* Colbits Mapping:
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* Colbits Mapping:
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* 2'b00 - 8 Bit
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* 2'b00 - 8 Bit
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* 2'b01 - 16 Bit
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* 2'b01 - 16 Bit
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* 2'b10 - 10 Bit
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* 2'b10 - 10 Bit
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* 2'b11 - 11 Bits
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* 2'b11 - 11 Bits
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************************/
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************************/
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r2b_caddr <= (cfg_colbits == 2'b00) ? {4'b0, map_address[7:0]} :
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r2b_caddr <= (cfg_colbits == 2'b00) ? {4'b0, map_address[7:0]} :
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(cfg_colbits == 2'b01) ? {3'b0, map_address[8:0]} :
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(cfg_colbits == 2'b01) ? {3'b0, map_address[8:0]} :
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(cfg_colbits == 2'b10) ? {2'b0, map_address[9:0]} : {1'b0, map_address[10:0]};
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(cfg_colbits == 2'b10) ? {2'b0, map_address[9:0]} : {1'b0, map_address[10:0]};
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|
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r2b_raddr <= (cfg_colbits == 2'b00) ? map_address[21:10] :
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r2b_raddr <= (cfg_colbits == 2'b00) ? map_address[21:10] :
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(cfg_colbits == 2'b01) ? map_address[22:11] :
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(cfg_colbits == 2'b01) ? map_address[22:11] :
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(cfg_colbits == 2'b10) ? map_address[23:12] : map_address[24:13];
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(cfg_colbits == 2'b10) ? map_address[23:12] : map_address[24:13];
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end
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end
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endmodule // sdr_req_gen
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endmodule // sdr_req_gen
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