| Line 114... |
Line 114... |
parameter APP_RW = 9; // Application Request Width
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parameter APP_RW = 9; // Application Request Width
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_BW = 2; // SDR Byte Width
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parameter SDR_BW = 2; // SDR Byte Width
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// 12 bit subtractor is not feasibile for FPGA, so changed to 8 bits
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parameter REQ_BW = (`TARGET_DESIGN == `FPGA) ? 8 : 12; // Request Width
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input clk ;
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input clk ;
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input reset_n ;
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input reset_n ;
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input [1:0] cfg_colbits ; // 2'b00 - 8 Bit column address, 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
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input [1:0] cfg_colbits ; // 2'b00 - 8 Bit column address, 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
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output r2b_wrap ; // 1 - Wrap the Address at the page boundary.
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output r2b_wrap ; // 1 - Wrap the Address at the page boundary.
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output [`SDR_REQ_ID_W-1:0] r2b_req_id;
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output [`SDR_REQ_ID_W-1:0] r2b_req_id;
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output [1:0] r2b_ba ; // Bank Address
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output [1:0] r2b_ba ; // Bank Address
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output [11:0] r2b_raddr ; // Row Address
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output [11:0] r2b_raddr ; // Row Address
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output [11:0] r2b_caddr ; // Column Address
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output [11:0] r2b_caddr ; // Column Address
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output [REQ_BW-1:0] r2b_len ; // Burst Length
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output [`REQ_BW-1:0] r2b_len ; // Burst Length
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input b2r_ack ; // Request Ack
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input b2r_ack ; // Request Ack
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input b2r_arb_ok ; // Bank controller fifo is not full and ready to accept the command
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input b2r_arb_ok ; // Bank controller fifo is not full and ready to accept the command
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//
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//
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input [1:0] sdr_width; // 2'b00 - 32 Bit, 2'b01 - 16 Bit, 2'b1x - 8Bit
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input [1:0] sdr_width; // 2'b00 - 32 Bit, 2'b01 - 16 Bit, 2'b1x - 8Bit
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Line 156... |
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reg req_st, next_req_st;
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reg req_st, next_req_st;
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reg r2x_idle, req_ack, r2b_req, r2b_start,
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reg r2x_idle, req_ack, r2b_req, r2b_start,
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r2b_write, req_idle, req_ld, lcl_wrap;
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r2b_write, req_idle, req_ld, lcl_wrap;
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reg [`SDR_REQ_ID_W-1:0] r2b_req_id;
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reg [`SDR_REQ_ID_W-1:0] r2b_req_id;
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reg [REQ_BW-1:0] lcl_req_len;
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reg [`REQ_BW-1:0] lcl_req_len;
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wire r2b_last, page_ovflw;
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wire r2b_last, page_ovflw;
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wire [REQ_BW-1:0] r2b_len, next_req_len;
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wire [`REQ_BW-1:0] r2b_len, next_req_len;
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wire [12:0] max_r2b_len;
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wire [12:0] max_r2b_len;
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reg [12:0] max_r2b_len_r;
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reg [12:0] max_r2b_len_r;
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reg [1:0] r2b_ba;
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reg [1:0] r2b_ba;
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reg [11:0] r2b_raddr;
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reg [11:0] r2b_raddr;
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// if the current burst cross the page boundary.
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// if the current burst cross the page boundary.
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assign page_ovflw = ({1'b0, lcl_req_len} > max_r2b_len_r) ? ~lcl_wrap : 1'b0;
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assign page_ovflw = ({1'b0, lcl_req_len} > max_r2b_len_r) ? ~lcl_wrap : 1'b0;
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assign r2b_len = (page_ovflw) ? max_r2b_len_r : lcl_req_len;
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assign r2b_len = (page_ovflw) ? max_r2b_len_r : lcl_req_len;
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assign next_req_len = lcl_req_len - r2b_len;
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assign next_req_len = lcl_req_len - max_r2b_len_r;
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assign next_sdr_addr = curr_sdr_addr + r2b_len;
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assign next_sdr_addr = curr_sdr_addr + max_r2b_len_r;
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assign r2b_wrap = lcl_wrap;
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assign r2b_wrap = lcl_wrap;
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assign r2b_last = ~page_ovflw;
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assign r2b_last = ~page_ovflw;
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