| Line 9... |
Line 9... |
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Address Generation Based on cfg_colbits
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Address Generation Based on cfg_colbits
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cfg_colbits= 2'b00
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cfg_colbits= 2'b00
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Address[7:0] - Column Address
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Address[7:0] - Column Address
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Address[9:8] - Bank Address
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Address[9:8] - Bank Address
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Address[21:10] - Row Address
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Address[22:10] - Row Address
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cfg_colbits= 2'b01
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cfg_colbits= 2'b01
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Address[8:0] - Column Address
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Address[8:0] - Column Address
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Address[10:9] - Bank Address
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Address[10:9] - Bank Address
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Address[22:11] - Row Address
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Address[23:11] - Row Address
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cfg_colbits= 2'b10
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cfg_colbits= 2'b10
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Address[9:0] - Column Address
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Address[9:0] - Column Address
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Address[11:10] - Bank Address
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Address[11:10] - Bank Address
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Address[23:12] - Row Address
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Address[24:12] - Row Address
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cfg_colbits= 2'b11
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cfg_colbits= 2'b11
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Address[10:0] - Column Address
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Address[10:0] - Column Address
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Address[12:11] - Bank Address
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Address[12:11] - Bank Address
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Address[24:13] - Row Address
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Address[25:13] - Row Address
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The SDRAMs are operated in 4 beat burst mode.
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The SDRAMs are operated in 4 beat burst mode.
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If Wrap = 0;
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If Wrap = 0;
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If the current burst cross the page boundary, then this block split the request
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If the current burst cross the page boundary, then this block split the request
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| Line 106... |
Line 106... |
r2b_write, // write request
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r2b_write, // write request
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b2r_ack,
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b2r_ack,
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b2r_arb_ok
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b2r_arb_ok
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);
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);
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parameter APP_AW = 25; // Application Address Width
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parameter APP_AW = 26; // Application Address Width
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parameter APP_DW = 32; // Application Data Width
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parameter APP_DW = 32; // Application Data Width
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parameter APP_BW = 4; // Application Byte Width
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parameter APP_BW = 4; // Application Byte Width
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parameter APP_RW = 9; // Application Request Width
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parameter APP_RW = 9; // Application Request Width
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_DW = 16; // SDR Data Width
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| Line 137... |
Line 137... |
output r2b_last ; // Last Junk of the Burst Access
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output r2b_last ; // Last Junk of the Burst Access
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output r2b_write ; // 1 - Write, 0 - Read
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output r2b_write ; // 1 - Write, 0 - Read
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output r2b_wrap ; // 1 - Wrap the Address at the page boundary.
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output r2b_wrap ; // 1 - Wrap the Address at the page boundary.
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output [`SDR_REQ_ID_W-1:0] r2b_req_id;
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output [`SDR_REQ_ID_W-1:0] r2b_req_id;
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output [1:0] r2b_ba ; // Bank Address
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output [1:0] r2b_ba ; // Bank Address
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output [11:0] r2b_raddr ; // Row Address
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output [12:0] r2b_raddr ; // Row Address
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output [11:0] r2b_caddr ; // Column Address
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output [12:0] r2b_caddr ; // Column Address
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output [`REQ_BW-1:0] r2b_len ; // Burst Length
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output [`REQ_BW-1:0] r2b_len ; // Burst Length
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input b2r_ack ; // Request Ack
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input b2r_ack ; // Request Ack
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input b2r_arb_ok ; // Bank controller fifo is not full and ready to accept the command
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input b2r_arb_ok ; // Bank controller fifo is not full and ready to accept the command
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//
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//
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input [1:0] sdr_width; // 2'b00 - 32 Bit, 2'b01 - 16 Bit, 2'b1x - 8Bit
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input [1:0] sdr_width; // 2'b00 - 32 Bit, 2'b01 - 16 Bit, 2'b1x - 8Bit
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| Line 166... |
Line 166... |
wire [`REQ_BW-1:0] r2b_len, next_req_len;
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wire [`REQ_BW-1:0] r2b_len, next_req_len;
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wire [12:0] max_r2b_len;
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wire [12:0] max_r2b_len;
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reg [12:0] max_r2b_len_r;
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reg [12:0] max_r2b_len_r;
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reg [1:0] r2b_ba;
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reg [1:0] r2b_ba;
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reg [11:0] r2b_raddr;
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reg [12:0] r2b_raddr;
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reg [11:0] r2b_caddr;
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reg [12:0] r2b_caddr;
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reg [APP_AW-1:0] curr_sdr_addr ;
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reg [APP_AW-1:0] curr_sdr_addr ;
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wire [APP_AW-1:0] next_sdr_addr ;
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wire [APP_AW-1:0] next_sdr_addr ;
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| Line 326... |
Line 326... |
* 2'b00 - 8 Bit
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* 2'b00 - 8 Bit
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* 2'b01 - 16 Bit
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* 2'b01 - 16 Bit
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* 2'b10 - 10 Bit
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* 2'b10 - 10 Bit
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* 2'b11 - 11 Bits
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* 2'b11 - 11 Bits
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************************/
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************************/
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r2b_caddr <= (cfg_colbits == 2'b00) ? {4'b0, map_address[7:0]} :
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r2b_caddr <= (cfg_colbits == 2'b00) ? {5'b0, map_address[7:0]} :
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(cfg_colbits == 2'b01) ? {3'b0, map_address[8:0]} :
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(cfg_colbits == 2'b01) ? {4'b0, map_address[8:0]} :
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(cfg_colbits == 2'b10) ? {2'b0, map_address[9:0]} : {1'b0, map_address[10:0]};
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(cfg_colbits == 2'b10) ? {3'b0, map_address[9:0]} : {2'b0, map_address[10:0]};
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r2b_raddr <= (cfg_colbits == 2'b00) ? map_address[21:10] :
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r2b_raddr <= (cfg_colbits == 2'b00) ? map_address[22:10] :
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(cfg_colbits == 2'b01) ? map_address[22:11] :
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(cfg_colbits == 2'b01) ? map_address[23:11] :
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(cfg_colbits == 2'b10) ? map_address[23:12] : map_address[24:13];
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(cfg_colbits == 2'b10) ? map_address[24:12] : map_address[25:13];
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end
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end
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endmodule // sdr_req_gen
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endmodule // sdr_req_gen
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No newline at end of file
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