| Line 133... |
Line 133... |
parameter APP_DW = 32; // Application Data Width
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parameter APP_DW = 32; // Application Data Width
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parameter APP_BW = 4; // Application Byte Width
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parameter APP_BW = 4; // Application Byte Width
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_BW = 2; // SDR Byte Width
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parameter SDR_BW = 2; // SDR Byte Width
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parameter REQ_BW = 12; // Request Width
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// 12 bit subtractor is not feasibile for FPGA, so changed to 8 bits
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parameter REQ_BW = (`TARGET_DESIGN == `FPGA) ? 8 : 12; // Request Width
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input clk, reset_n;
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input clk, reset_n;
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/* Req from bank_ctl */
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/* Req from bank_ctl */
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| Line 239... |
Line 240... |
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assign xfr_cmd = (sel_mgmt) ? mgmt_cmd :
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assign xfr_cmd = (sel_mgmt) ? mgmt_cmd :
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(sel_b2x) ? b2x_sdr_cmd : i_xfr_cmd;
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(sel_b2x) ? b2x_sdr_cmd : i_xfr_cmd;
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assign xfr_addr = (sel_mgmt) ? mgmt_addr :
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assign xfr_addr = (sel_mgmt) ? mgmt_addr :
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(sel_b2x) ? b2x_addr : xfr_caddr;
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(sel_b2x) ? b2x_addr : xfr_caddr+1;
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assign mgmt_ack = sel_mgmt;
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assign mgmt_ack = sel_mgmt;
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assign x2b_ack = sel_b2x;
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assign x2b_ack = sel_b2x;
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assign ld_xfr = sel_b2x & (b2x_read | b2x_write);
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assign ld_xfr = sel_b2x & (b2x_read | b2x_write);
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assign xfr_len = (ld_xfr) ? b2x_len : l_len;
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assign xfr_len = (ld_xfr) ? b2x_len : l_len;
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assign next_xfr_len = (xfr_end) ? xfr_len : xfr_len - 1;
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//assign next_xfr_len = (l_xfr_end && !ld_xfr) ? l_len : xfr_len - 1;
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assign next_xfr_len = (ld_xfr) ? b2x_len :
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(l_xfr_end) ? l_len: l_len - 1;
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assign d_rd_next = (cas_latency == 2'b01) ? l_rd_next[2] :
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assign d_rd_next = (cas_latency == 2'b01) ? l_rd_next[2] :
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(cas_latency == 2'b10) ? l_rd_next[3] :
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(cas_latency == 2'b10) ? l_rd_next[3] :
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l_rd_next[4];
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l_rd_next[4];
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| Line 271... |
Line 274... |
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assign dt_next = wr_next | d_rd_next;
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assign dt_next = wr_next | d_rd_next;
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assign xfr_end = ~|xfr_len;
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assign xfr_end = ~|xfr_len;
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assign l_xfr_end = ~|l_len;
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assign l_xfr_end = ~|(l_len-1);
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assign rd_start = ld_xfr & b2x_read & b2x_start;
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assign rd_start = ld_xfr & b2x_read & b2x_start;
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assign wr_start = ld_xfr & b2x_write & b2x_start;
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assign wr_start = ld_xfr & b2x_write & b2x_start;
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Line 293... |
(sel_b2x) ? b2x_ba : l_ba;
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(sel_b2x) ? b2x_ba : l_ba;
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assign xfr_wrap = (ld_xfr) ? b2x_wrap : l_wrap;
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assign xfr_wrap = (ld_xfr) ? b2x_wrap : l_wrap;
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// assign burst_bdry = ~|xfr_caddr[2:0];
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// assign burst_bdry = ~|xfr_caddr[2:0];
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assign burst_bdry = ~|xfr_caddr[1:0];
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wire [1:0] xfr_caddr_lsb = (xfr_caddr[1:0]+1);
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assign burst_bdry = ~|(xfr_caddr_lsb[1:0]);
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always @ (posedge clk) begin
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always @ (posedge clk) begin
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if (~reset_n) begin
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if (~reset_n) begin
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xfr_caddr <= 12'b0;
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xfr_caddr <= 12'b0;
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l_start <= 1'b0;
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l_start <= 1'b0;
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| Line 310... |
Line 314... |
d_act_cmd <= 1'b0;
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d_act_cmd <= 1'b0;
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xfr_st <= `XFR_IDLE;
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xfr_st <= `XFR_IDLE;
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end // if (~reset_n)
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end // if (~reset_n)
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else begin
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else begin
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xfr_caddr <= (ld_xfr) ? b2x_addr + 12'h1 :
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xfr_caddr <= (ld_xfr) ? b2x_addr :
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(rd_next | wr_next) ? xfr_caddr + 12'h1 :
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(rd_next | wr_next) ? xfr_caddr + 1 : xfr_caddr;
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xfr_caddr;
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l_start <= (dt_next) ? 1'b0 :
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l_start <= (dt_next) ? 1'b0 :
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(ld_xfr) ? b2x_start : l_start;
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(ld_xfr) ? b2x_start : l_start;
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l_last <= (ld_xfr) ? b2x_last : l_last;
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l_last <= (ld_xfr) ? b2x_last : l_last;
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l_wrap <= (ld_xfr) ? b2x_wrap : l_wrap;
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l_wrap <= (ld_xfr) ? b2x_wrap : l_wrap;
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l_id <= (ld_xfr) ? b2x_id : l_id;
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l_id <= (ld_xfr) ? b2x_id : l_id;
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| Line 356... |
Line 359... |
`XFR_READ : begin
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`XFR_READ : begin
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rd_next = ~l_xfr_end |
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rd_next = ~l_xfr_end |
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l_xfr_end & ~mgmt_req & b2x_req & b2x_read;
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l_xfr_end & ~mgmt_req & b2x_req & b2x_read;
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wr_next = 1'b0;
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wr_next = 1'b0;
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rdok = l_xfr_end & ~mgmt_req;
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rdok = l_xfr_end & ~mgmt_req;
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cb_pre_ok = l_xfr_end;
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// Break the timing path for FPGA Based Design
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cb_pre_ok = (`TARGET_DESIGN == `FPGA) ? 1'b0 : l_xfr_end;
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wrok = 1'b0;
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wrok = 1'b0;
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sel_mgmt = 1'b0;
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sel_mgmt = 1'b0;
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if (l_xfr_end) begin // end of transfer
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if (l_xfr_end) begin // end of transfer
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| Line 499... |
Line 503... |
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assign x2b_rdok = rdok;
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assign x2b_rdok = rdok;
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assign x2b_wrok = wrok;
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assign x2b_wrok = wrok;
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assign x2b_pre_ok[0] = (l_ba == 2'b00) ? cb_pre_ok : 1'b1;
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//assign x2b_pre_ok[0] = (l_ba == 2'b00) ? cb_pre_ok : 1'b1;
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assign x2b_pre_ok[1] = (l_ba == 2'b01) ? cb_pre_ok : 1'b1;
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//assign x2b_pre_ok[1] = (l_ba == 2'b01) ? cb_pre_ok : 1'b1;
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assign x2b_pre_ok[2] = (l_ba == 2'b10) ? cb_pre_ok : 1'b1;
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//assign x2b_pre_ok[2] = (l_ba == 2'b10) ? cb_pre_ok : 1'b1;
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assign x2b_pre_ok[3] = (l_ba == 2'b11) ? cb_pre_ok : 1'b1;
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//assign x2b_pre_ok[3] = (l_ba == 2'b11) ? cb_pre_ok : 1'b1;
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assign x2b_pre_ok[0] = cb_pre_ok;
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assign x2b_pre_ok[1] = cb_pre_ok;
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assign x2b_pre_ok[2] = cb_pre_ok;
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assign x2b_pre_ok[3] = cb_pre_ok;
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assign last_burst = (ld_xfr) ? b2x_last : l_last;
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assign last_burst = (ld_xfr) ? b2x_last : l_last;
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/************************************************************************/
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/************************************************************************/
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// APP Data I/F
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// APP Data I/F
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