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parameter APP_DW = 32; // Application Data Width
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parameter APP_DW = 32; // Application Data Width
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parameter APP_BW = 4; // Application Byte Width
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parameter APP_BW = 4; // Application Byte Width
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_BW = 2; // SDR Byte Width
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parameter SDR_BW = 2; // SDR Byte Width
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// 12 bit subtractor is not feasibile for FPGA, so changed to 8 bits
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parameter REQ_BW = (`TARGET_DESIGN == `FPGA) ? 8 : 12; // Request Width
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input clk, reset_n;
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input clk, reset_n;
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/* Req from bank_ctl */
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/* Req from bank_ctl */
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input b2x_req, b2x_start, b2x_last, b2x_tras_ok,
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input b2x_req, b2x_start, b2x_last, b2x_tras_ok,
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b2x_wrap, r2x_idle, b2x_idle;
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b2x_wrap, r2x_idle, b2x_idle;
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input [`SDR_REQ_ID_W-1:0] b2x_id;
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input [`SDR_REQ_ID_W-1:0] b2x_id;
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input [1:0] b2x_ba;
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input [1:0] b2x_ba;
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input [11:0] b2x_addr;
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input [11:0] b2x_addr;
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input [REQ_BW-1:0] b2x_len;
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input [`REQ_BW-1:0] b2x_len;
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input [1:0] b2x_cmd;
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input [1:0] b2x_cmd;
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output x2b_ack;
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output x2b_ack;
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/* Status to bank_ctl */
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/* Status to bank_ctl */
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output [3:0] x2b_pre_ok;
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output [3:0] x2b_pre_ok;
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wire [`SDR_REQ_ID_W-1:0] x2a_id;
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wire [`SDR_REQ_ID_W-1:0] x2a_id;
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reg [`SDR_REQ_ID_W-1:0] l_id;
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reg [`SDR_REQ_ID_W-1:0] l_id;
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wire [1:0] xfr_ba;
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wire [1:0] xfr_ba;
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reg [1:0] l_ba;
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reg [1:0] l_ba;
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wire [11:0] xfr_addr;
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wire [11:0] xfr_addr;
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wire [REQ_BW-1:0] xfr_len, next_xfr_len;
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wire [`REQ_BW-1:0] xfr_len, next_xfr_len;
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reg [REQ_BW-1:0] l_len;
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reg [`REQ_BW-1:0] l_len;
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reg mgmt_idle, mgmt_req;
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reg mgmt_idle, mgmt_req;
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reg [3:0] mgmt_cmd;
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reg [3:0] mgmt_cmd;
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reg [11:0] mgmt_addr;
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reg [11:0] mgmt_addr;
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reg [1:0] mgmt_ba;
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reg [1:0] mgmt_ba;
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assign rd_start = ld_xfr & b2x_read & b2x_start;
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assign rd_start = ld_xfr & b2x_read & b2x_start;
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assign wr_start = ld_xfr & b2x_write & b2x_start;
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assign wr_start = ld_xfr & b2x_write & b2x_start;
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assign rd_last = rd_next & last_burst & ~|xfr_len[REQ_BW-1:1];
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assign rd_last = rd_next & last_burst & ~|xfr_len[`REQ_BW-1:1];
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//assign wr_last = wr_next & last_burst & ~|xfr_len[APP_RW-1:1];
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//assign wr_last = wr_next & last_burst & ~|xfr_len[APP_RW-1:1];
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assign wr_last = last_burst & ~|xfr_len[REQ_BW-1:1];
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assign wr_last = last_burst & ~|xfr_len[`REQ_BW-1:1];
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//assign xfr_ba = (ld_xfr) ? b2x_ba : l_ba;
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//assign xfr_ba = (ld_xfr) ? b2x_ba : l_ba;
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assign xfr_ba = (sel_mgmt) ? mgmt_ba :
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assign xfr_ba = (sel_mgmt) ? mgmt_ba :
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(sel_b2x) ? b2x_ba : l_ba;
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(sel_b2x) ? b2x_ba : l_ba;
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