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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_xfr_ctl.v] - Diff between revs 64 and 69

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Rev 64 Rev 69
Line 138... Line 138... 
   /* Req from bank_ctl */
 
   /* Req from bank_ctl */
 
input                   b2x_req, b2x_start, b2x_last, b2x_tras_ok,
 
input                   b2x_req, b2x_start, b2x_last, b2x_tras_ok,
 
                                b2x_wrap, r2x_idle, b2x_idle;
 
                                b2x_wrap, r2x_idle, b2x_idle;
 
input [`SDR_REQ_ID_W-1:0]        b2x_id;
 
input [`SDR_REQ_ID_W-1:0]        b2x_id;
 
input [1:0]                      b2x_ba;
 
input [1:0]                      b2x_ba;
 
input [11:0]             b2x_addr;
 
input [12:0]             b2x_addr;
 
input [`REQ_BW-1:0]      b2x_len;
 
input [`REQ_BW-1:0]      b2x_len;
 
input [1:0]                      b2x_cmd;
 
input [1:0]                      b2x_cmd;
 
output                  x2b_ack;
 
output                  x2b_ack;
 
 
 
 
 
/* Status to bank_ctl */
 
/* Status to bank_ctl */
Line 161... Line 161... 
/* Interface to SDRAMs */
 
/* Interface to SDRAMs */
 
output                  sdr_cs_n, sdr_cke, sdr_ras_n, sdr_cas_n,
 
output                  sdr_cs_n, sdr_cke, sdr_ras_n, sdr_cas_n,
 
                                sdr_we_n;
 
                                sdr_we_n;
 
output [SDR_BW-1:0]      sdr_dqm;
 
output [SDR_BW-1:0]      sdr_dqm;
 
output [1:0]             sdr_ba;
 
output [1:0]             sdr_ba;
 
output [11:0]            sdr_addr;
 
output [12:0]            sdr_addr;
 
input [SDR_DW-1:0]       sdr_din;
 
input [SDR_DW-1:0]       sdr_din;
 
output [SDR_DW-1:0]      sdr_dout;
 
output [SDR_DW-1:0]      sdr_dout;
 
output [SDR_BW-1:0]      sdr_den_n;
 
output [SDR_BW-1:0]      sdr_den_n;
 
 
 
 
 
   output [1:0]                  xfr_bank_sel;
 
   output [1:0]                  xfr_bank_sel;
Line 185... Line 185... 
   `define XFR_WRITE       2'b01
 
   `define XFR_WRITE       2'b01
 
   `define XFR_READ        2'b10
 
   `define XFR_READ        2'b10
 
   `define XFR_RDWT        2'b11
 
   `define XFR_RDWT        2'b11
 
 
 
 
 
   reg [1:0]                     xfr_st, next_xfr_st;
 
   reg [1:0]                     xfr_st, next_xfr_st;
 
   reg [11:0]                    xfr_caddr;
 
   reg [12:0]                    xfr_caddr;
 
   wire                         last_burst;
 
   wire                         last_burst;
 
   wire                         x2a_rdstart, x2a_wrstart, x2a_rdlast, x2a_wrlast;
 
   wire                         x2a_rdstart, x2a_wrstart, x2a_rdlast, x2a_wrlast;
 
   reg                          l_start, l_last, l_wrap;
 
   reg                          l_start, l_last, l_wrap;
 
   wire [`SDR_REQ_ID_W-1:0]      x2a_id;
 
   wire [`SDR_REQ_ID_W-1:0]      x2a_id;
 
   reg [`SDR_REQ_ID_W-1:0]       l_id;
 
   reg [`SDR_REQ_ID_W-1:0]       l_id;
 
   wire [1:0]                    xfr_ba;
 
   wire [1:0]                    xfr_ba;
 
   reg [1:0]                     l_ba;
 
   reg [1:0]                     l_ba;
 
   wire [11:0]                   xfr_addr;
 
   wire [12:0]                   xfr_addr;
 
   wire [`REQ_BW-1:0]    xfr_len, next_xfr_len;
 
   wire [`REQ_BW-1:0]    xfr_len, next_xfr_len;
 
   reg [`REQ_BW-1:0]     l_len;
 
   reg [`REQ_BW-1:0]     l_len;
 
 
 
 
 
   reg                          mgmt_idle, mgmt_req;
 
   reg                          mgmt_idle, mgmt_req;
 
   reg [3:0]                     mgmt_cmd;
 
   reg [3:0]                     mgmt_cmd;
 
   reg [11:0]                    mgmt_addr;
 
   reg [12:0]                    mgmt_addr;
 
   reg [1:0]                     mgmt_ba;
 
   reg [1:0]                     mgmt_ba;
 
 
 
 
 
   reg                          sel_mgmt, sel_b2x;
 
   reg                          sel_mgmt, sel_b2x;
 
   reg                          cb_pre_ok, rdok, wrok, wr_next,
 
   reg                          cb_pre_ok, rdok, wrok, wr_next,
 
                                rd_next, sdr_init_done, act_cmd, d_act_cmd;
 
                                rd_next, sdr_init_done, act_cmd, d_act_cmd;
Line 300... Line 300... 
   wire [1:0] xfr_caddr_lsb = (xfr_caddr[1:0]+1);
 
   wire [1:0] xfr_caddr_lsb = (xfr_caddr[1:0]+1);
 
   assign burst_bdry = ~|(xfr_caddr_lsb[1:0]);
 
   assign burst_bdry = ~|(xfr_caddr_lsb[1:0]);
 
 
 
 
 
   always @ (posedge clk) begin
 
   always @ (posedge clk) begin
 
      if (~reset_n) begin
 
      if (~reset_n) begin
 
         xfr_caddr <= 12'b0;
 
         xfr_caddr <= 13'b0;
 
         l_start <= 1'b0;
 
         l_start <= 1'b0;
 
         l_last <= 1'b0;
 
         l_last <= 1'b0;
 
         l_wrap <= 1'b0;
 
         l_wrap <= 1'b0;
 
         l_id <= 0;
 
         l_id <= 0;
 
         l_ba <= 0;
 
         l_ba <= 0;
Line 543... Line 543... 
 
 
 
 
   reg                          sdr_cs_n, sdr_cke, sdr_ras_n, sdr_cas_n,
 
   reg                          sdr_cs_n, sdr_cke, sdr_ras_n, sdr_cas_n,
 
                                sdr_we_n;
 
                                sdr_we_n;
 
   reg [SDR_BW-1:0]      sdr_dqm;
 
   reg [SDR_BW-1:0]      sdr_dqm;
 
   reg [1:0]                     sdr_ba;
 
   reg [1:0]                     sdr_ba;
 
   reg [11:0]                    sdr_addr;
 
   reg [12:0]                    sdr_addr;
 
   reg [SDR_DW-1:0]      sdr_dout;
 
   reg [SDR_DW-1:0]      sdr_dout;
 
   reg [SDR_BW-1:0]      sdr_den_n;
 
   reg [SDR_BW-1:0]      sdr_den_n;
 
 
 
 
 
   always @ (posedge clk)
 
   always @ (posedge clk)
 
      if (~reset_n) begin
 
      if (~reset_n) begin
Line 643... Line 643... 
        `MGM_POWERUP : begin
 
        `MGM_POWERUP : begin
 
           mgmt_idle = 1'b0;
 
           mgmt_idle = 1'b0;
 
           mgmt_req = 1'b0;
 
           mgmt_req = 1'b0;
 
           mgmt_cmd = `SDR_DESEL;
 
           mgmt_cmd = `SDR_DESEL;
 
           mgmt_ba = 2'b0;
 
           mgmt_ba = 2'b0;
 
           mgmt_addr = 12'h400;    // A10 = 1 => all banks
 
           mgmt_addr = 13'h400;    // A10 = 1 => all banks
 
           ld_tmr0 = 1'b0;
 
           ld_tmr0 = 1'b0;
 
           tmr0_d = 4'b0;
 
           tmr0_d = 4'b0;
 
           dec_cntr1 = 1'b0;
 
           dec_cntr1 = 1'b0;
 
           ld_cntr1 = 1'b1;
 
           ld_cntr1 = 1'b1;
 
           cntr1_d = 4'hf; // changed for sdrams with higher refresh cycles during initialization
 
           cntr1_d = 4'hf; // changed for sdrams with higher refresh cycles during initialization
Line 658... Line 658... 
        `MGM_PRECHARGE : begin     // Precharge all banks
 
        `MGM_PRECHARGE : begin     // Precharge all banks
 
           mgmt_idle = 1'b0;
 
           mgmt_idle = 1'b0;
 
           mgmt_req = 1'b1;
 
           mgmt_req = 1'b1;
 
           mgmt_cmd = (precharge_ok) ? `SDR_PRECHARGE : `SDR_DESEL;
 
           mgmt_cmd = (precharge_ok) ? `SDR_PRECHARGE : `SDR_DESEL;
 
           mgmt_ba = 2'b0;
 
           mgmt_ba = 2'b0;
 
           mgmt_addr = 12'h400;    // A10 = 1 => all banks
 
           mgmt_addr = 13'h400;    // A10 = 1 => all banks
 
           ld_tmr0 = mgmt_ack;
 
           ld_tmr0 = mgmt_ack;
 
           tmr0_d = trp_delay;
 
           tmr0_d = trp_delay;
 
           ld_cntr1 = 1'b0;
 
           ld_cntr1 = 1'b0;
 
           cntr1_d = 4'h7;
 
           cntr1_d = 4'h7;
 
           dec_cntr1 = 1'b0;
 
           dec_cntr1 = 1'b0;
Line 673... Line 673... 
        `MGM_PCHWT : begin         // Wait for Trp
 
        `MGM_PCHWT : begin         // Wait for Trp
 
           mgmt_idle = 1'b0;
 
           mgmt_idle = 1'b0;
 
           mgmt_req = 1'b1;
 
           mgmt_req = 1'b1;
 
           mgmt_cmd = `SDR_DESEL;
 
           mgmt_cmd = `SDR_DESEL;
 
           mgmt_ba = 2'b0;
 
           mgmt_ba = 2'b0;
 
           mgmt_addr = 12'h400;    // A10 = 1 => all banks
 
           mgmt_addr = 13'h400;    // A10 = 1 => all banks
 
           ld_tmr0 = 1'b0;
 
           ld_tmr0 = 1'b0;
 
           tmr0_d = trp_delay;
 
           tmr0_d = trp_delay;
 
           ld_cntr1 = 1'b0;
 
           ld_cntr1 = 1'b0;
 
           cntr1_d = 4'b0;
 
           cntr1_d = 4'b0;
 
           dec_cntr1 = 1'b0;
 
           dec_cntr1 = 1'b0;
Line 688... Line 688... 
        `MGM_REFRESH : begin       // Refresh
 
        `MGM_REFRESH : begin       // Refresh
 
           mgmt_idle = 1'b0;
 
           mgmt_idle = 1'b0;
 
           mgmt_req = 1'b1;
 
           mgmt_req = 1'b1;
 
           mgmt_cmd = `SDR_REFRESH;
 
           mgmt_cmd = `SDR_REFRESH;
 
           mgmt_ba = 2'b0;
 
           mgmt_ba = 2'b0;
 
           mgmt_addr = 12'h400;    // A10 = 1 => all banks
 
           mgmt_addr = 13'h400;    // A10 = 1 => all banks
 
           ld_tmr0 = mgmt_ack;
 
           ld_tmr0 = mgmt_ack;
 
           tmr0_d = trcar_delay;
 
           tmr0_d = trcar_delay;
 
           dec_cntr1 = mgmt_ack;
 
           dec_cntr1 = mgmt_ack;
 
           ld_cntr1 = 1'b0;
 
           ld_cntr1 = 1'b0;
 
           cntr1_d = 4'h7;
 
           cntr1_d = 4'h7;
Line 703... Line 703... 
        `MGM_REFWT : begin         // Wait for trcar
 
        `MGM_REFWT : begin         // Wait for trcar
 
           mgmt_idle = 1'b0;
 
           mgmt_idle = 1'b0;
 
           mgmt_req = 1'b1;
 
           mgmt_req = 1'b1;
 
           mgmt_cmd = `SDR_DESEL;
 
           mgmt_cmd = `SDR_DESEL;
 
           mgmt_ba = 2'b0;
 
           mgmt_ba = 2'b0;
 
           mgmt_addr = 12'h400;    // A10 = 1 => all banks
 
           mgmt_addr = 13'h400;    // A10 = 1 => all banks
 
           ld_tmr0 = 1'b0;
 
           ld_tmr0 = 1'b0;
 
           tmr0_d = trcar_delay;
 
           tmr0_d = trcar_delay;
 
           dec_cntr1 = 1'b0;
 
           dec_cntr1 = 1'b0;
 
           ld_cntr1 = 1'b0;
 
           ld_cntr1 = 1'b0;
 
           cntr1_d = 4'h7;
 
           cntr1_d = 4'h7;
Line 735... Line 735... 
        `MGM_MODE_WT : begin       // Wait for tMRD
 
        `MGM_MODE_WT : begin       // Wait for tMRD
 
           mgmt_idle = 1'b0;
 
           mgmt_idle = 1'b0;
 
           mgmt_req = 1'b1;
 
           mgmt_req = 1'b1;
 
           mgmt_cmd = `SDR_DESEL;
 
           mgmt_cmd = `SDR_DESEL;
 
           mgmt_ba = 2'bx;
 
           mgmt_ba = 2'bx;
 
           mgmt_addr = 12'bx;
 
           mgmt_addr = 13'bx;
 
           ld_tmr0 = 1'b0;
 
           ld_tmr0 = 1'b0;
 
           tmr0_d = 4'h7;
 
           tmr0_d = 4'h7;
 
           dec_cntr1 = 1'b0;
 
           dec_cntr1 = 1'b0;
 
           ld_cntr1 = 1'b0;
 
           ld_cntr1 = 1'b0;
 
           cntr1_d = 4'h7;
 
           cntr1_d = 4'h7;
Line 750... Line 750... 
        `MGM_ACTIVE : begin        // Wait for ref_req
 
        `MGM_ACTIVE : begin        // Wait for ref_req
 
           mgmt_idle = ~ref_req;
 
           mgmt_idle = ~ref_req;
 
           mgmt_req = 1'b0;
 
           mgmt_req = 1'b0;
 
           mgmt_cmd = `SDR_DESEL;
 
           mgmt_cmd = `SDR_DESEL;
 
           mgmt_ba = 2'bx;
 
           mgmt_ba = 2'bx;
 
           mgmt_addr = 12'bx;
 
           mgmt_addr = 13'bx;
 
           ld_tmr0 = 1'b0;
 
           ld_tmr0 = 1'b0;
 
           tmr0_d = 4'h7;
 
           tmr0_d = 4'h7;
 
           dec_cntr1 = 1'b0;
 
           dec_cntr1 = 1'b0;
 
           ld_cntr1 = ref_req;
 
           ld_cntr1 = ref_req;
 
           cntr1_d = rfsh_row_cnt;
 
           cntr1_d = rfsh_row_cnt;

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