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Line 3... |
SDRAM Controller top File
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SDRAM Controller top File
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This file is part of the sdram controller project
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This file is part of the sdram controller project
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http://www.opencores.org/cores/sdr_ctrl/
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http://www.opencores.org/cores/sdr_ctrl/
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Description: SDRAM Controller Core Module
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Description: SDRAM Controller Top Module.
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2 types of SDRAMs are supported, 1Mx16 2 bank, or 4Mx16 4 bank.
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Support 81/6/32 Bit SDRAM.
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Column Address is Programmable
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Bank Bit are 2 Bit
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Row Bits are 12 Bits
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This block integrate following sub modules
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This block integrate following sub modules
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sdrc_core
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sdrc_core
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SDRAM Controller file
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SDRAM Controller file
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wb2sdrc
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wb2sdrc
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Line 102... |
cfg_sdr_trcd_d,
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cfg_sdr_trcd_d,
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cfg_sdr_cas,
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cfg_sdr_cas,
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cfg_sdr_trcar_d,
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cfg_sdr_trcar_d,
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cfg_sdr_twr_d,
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cfg_sdr_twr_d,
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cfg_sdr_rfsh,
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cfg_sdr_rfsh,
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cfg_sdr_rfmax);
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cfg_sdr_rfmax
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);
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parameter APP_AW = 30; // Application Address Width
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parameter APP_AW = 30; // Application Address Width
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parameter APP_DW = 32; // Application Data Width
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parameter APP_DW = 32; // Application Data Width
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parameter APP_BW = 4; // Application Byte Width
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parameter APP_BW = 4; // Application Byte Width
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parameter APP_RW = 9; // Application Request Width
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parameter APP_RW = 9; // Application Request Width
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Line 124... |
// ----------------------------------------------
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// ----------------------------------------------
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input sdram_clk ; // SDRAM Clock
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input sdram_clk ; // SDRAM Clock
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input sdram_pad_clk ; // SDRAM Clock from Pad, used for registering Read Data
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input sdram_pad_clk ; // SDRAM Clock from Pad, used for registering Read Data
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input sdram_resetn ; // Reset Signal
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input sdram_resetn ; // Reset Signal
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input [1:0] sdr_width ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
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input [1:0] sdr_width ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
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input [1:0] cfg_colbits ; // 2'b00 - 8 Bit column address, 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
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input [1:0] cfg_colbits ; // 2'b00 - 8 Bit column address,
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// 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
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//--------------------------------------
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//--------------------------------------
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// Wish Bone Interface
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// Wish Bone Interface
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// -------------------------------------
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// -------------------------------------
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input wb_rst_i ;
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input wb_rst_i ;
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