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To Do:
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To Do:
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nothing
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nothing
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Author(s): Dinesh Annayya, dinesha@opencores.org
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Author(s): Dinesh Annayya, dinesha@opencores.org
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Version : 1.0 - 8th Jan 2012
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Version : 0.0 - 8th Jan 2012
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Initial version with 16/32 Bit SDRAM Support
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Initial version with 16/32 Bit SDRAM Support
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: 1.1 - 24th Jan 2012
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: 0.1 - 24th Jan 2012
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8 Bit SDRAM Support is added
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8 Bit SDRAM Support is added
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0.2 - 31st Jan 2012
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sdram_dq and sdram_pad_clk are internally generated
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Copyright (C) 2000 Authors and OPENCORES.ORG
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Copyright (C) 2000 Authors and OPENCORES.ORG
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This source file may be used and distributed without
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This source file may be used and distributed without
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from http://www.opencores.org/lgpl.shtml
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from http://www.opencores.org/lgpl.shtml
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*******************************************************************/
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*******************************************************************/
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`include "sdrc.def"
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`include "sdrc_define.v"
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module sdrc_top
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module sdrc_top
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(
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(
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sdr_width ,
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sdr_width ,
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cfg_colbits ,
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cfg_colbits ,
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wb_cti_i ,
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wb_cti_i ,
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/* Interface to SDRAMs */
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/* Interface to SDRAMs */
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sdram_clk ,
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sdram_clk ,
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sdram_pad_clk ,
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sdram_resetn ,
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sdram_resetn ,
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sdr_cs_n ,
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sdr_cs_n ,
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sdr_cke ,
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sdr_cke ,
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sdr_ras_n ,
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sdr_ras_n ,
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sdr_cas_n ,
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sdr_cas_n ,
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sdr_we_n ,
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sdr_we_n ,
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sdr_dqm ,
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sdr_dqm ,
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sdr_ba ,
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sdr_ba ,
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sdr_addr ,
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sdr_addr ,
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pad_sdr_din ,
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sdr_dq ,
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sdr_dout ,
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sdr_den_n ,
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/* Parameters */
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/* Parameters */
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sdr_init_done ,
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sdr_init_done ,
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cfg_req_depth , //how many req. buffer should hold
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cfg_req_depth , //how many req. buffer should hold
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cfg_sdr_en ,
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cfg_sdr_en ,
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//-----------------------------------------------
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//-----------------------------------------------
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// Global Variable
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// Global Variable
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// ----------------------------------------------
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// ----------------------------------------------
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input sdram_clk ; // SDRAM Clock
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input sdram_clk ; // SDRAM Clock
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input sdram_pad_clk ; // SDRAM Clock from Pad, used for registering Read Data
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input sdram_resetn ; // Reset Signal
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input sdram_resetn ; // Reset Signal
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input [1:0] sdr_width ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
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input [1:0] sdr_width ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
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input [1:0] cfg_colbits ; // 2'b00 - 8 Bit column address,
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input [1:0] cfg_colbits ; // 2'b00 - 8 Bit column address,
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// 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
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// 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
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output sdr_cas_n ; // SDRAM cas
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output sdr_cas_n ; // SDRAM cas
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output sdr_we_n ; // SDRAM write enable
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output sdr_we_n ; // SDRAM write enable
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output [SDR_BW-1:0] sdr_dqm ; // SDRAM Data Mask
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output [SDR_BW-1:0] sdr_dqm ; // SDRAM Data Mask
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output [1:0] sdr_ba ; // SDRAM Bank Enable
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output [1:0] sdr_ba ; // SDRAM Bank Enable
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output [11:0] sdr_addr ; // SDRAM Address
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output [11:0] sdr_addr ; // SDRAM Address
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input [SDR_DW-1:0] pad_sdr_din ; // SDRA Data Input
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inout [SDR_DW-1:0] sdr_dq ; // SDRA Data Input/output
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output [SDR_DW-1:0] sdr_dout ; // SDRAM Data Output
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output [SDR_BW-1:0] sdr_den_n ; // SDRAM Data Output enable
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//------------------------------------------------
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//------------------------------------------------
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// Configuration Parameter
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// Configuration Parameter
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//------------------------------------------------
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//------------------------------------------------
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output sdr_init_done ; // Indicate SDRAM Initialisation Done
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output sdr_init_done ; // Indicate SDRAM Initialisation Done
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wire app_rd_valid ; // sdr read valid
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wire app_rd_valid ; // sdr read valid
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wire app_last_rd ; // Indicate last Read of Burst Transfer
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wire app_last_rd ; // Indicate last Read of Burst Transfer
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wire [dw-1:0] app_wr_data ; // sdr write data
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wire [dw-1:0] app_wr_data ; // sdr write data
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wire [dw-1:0] app_rd_data ; // sdr read data
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wire [dw-1:0] app_rd_data ; // sdr read data
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/****************************************
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* These logic has to be implemented using Pads
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* **************************************/
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wire [SDR_DW-1:0] pad_sdr_din ; // SDRA Data Input
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wire [SDR_DW-1:0] sdr_dout ; // SDRAM Data Output
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wire [SDR_BW-1:0] sdr_den_n ; // SDRAM Data Output enable
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assign sdr_dq = (&sdr_den_n == 1'b0) ? sdr_dout : {SDR_DW{1'bz}};
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assign pad_sdr_din = sdr_dq;
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// sdram pad clock is routed back through pad
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// SDRAM Clock from Pad, used for registering Read Data
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wire #(1.0) sdram_pad_clk = sdram_clk;
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/************** Ends Here **************************/
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wb2sdrc u_wb2sdrc (
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wb2sdrc u_wb2sdrc (
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// WB bus
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// WB bus
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.wb_rst_i (wb_rst_i ) ,
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.wb_rst_i (wb_rst_i ) ,
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.wb_clk_i (wb_clk_i ) ,
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.wb_clk_i (wb_clk_i ) ,
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