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[/] [sdr_ctrl/] [trunk/] [rtl/] [top/] [sdrc_top.v] - Diff between revs 37 and 38

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Rev 37 Rev 38
Line 58... Line 58...
 
 
 
 
`include "sdrc_define.v"
`include "sdrc_define.v"
module sdrc_top
module sdrc_top
           (
           (
                    sdr_width           ,
                    cfg_sdr_width       ,
                    cfg_colbits         ,
                    cfg_colbits         ,
 
 
                // WB bus
                // WB bus
                    wb_rst_i            ,
                    wb_rst_i            ,
                    wb_clk_i            ,
                    wb_clk_i            ,
Line 121... Line 121...
//-----------------------------------------------
//-----------------------------------------------
// Global Variable
// Global Variable
// ----------------------------------------------
// ----------------------------------------------
input                   sdram_clk          ; // SDRAM Clock 
input                   sdram_clk          ; // SDRAM Clock 
input                   sdram_resetn       ; // Reset Signal
input                   sdram_resetn       ; // Reset Signal
input [1:0]             sdr_width          ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
input [1:0]             cfg_sdr_width      ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
input [1:0]             cfg_colbits        ; // 2'b00 - 8 Bit column address, 
input [1:0]             cfg_colbits        ; // 2'b00 - 8 Bit column address, 
                                             // 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
                                             // 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
 
 
//--------------------------------------
//--------------------------------------
// Wish Bone Interface
// Wish Bone Interface
Line 241... Line 241...
 
 
sdrc_core #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_sdrc_core (
sdrc_core #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_sdrc_core (
          .clk                (sdram_clk          ) ,
          .clk                (sdram_clk          ) ,
          .pad_clk            (sdram_pad_clk      ) ,
          .pad_clk            (sdram_pad_clk      ) ,
          .reset_n            (sdram_resetn       ) ,
          .reset_n            (sdram_resetn       ) ,
          .sdr_width          (sdr_width          ) ,
          .sdr_width          (cfg_sdr_width      ) ,
          .cfg_colbits        (cfg_colbits        ) ,
          .cfg_colbits        (cfg_colbits        ) ,
 
 
                /* Request from app */
                /* Request from app */
          .app_req            (app_req            ) ,// Transfer Request
          .app_req            (app_req            ) ,// Transfer Request
          .app_req_addr       (app_req_addr       ) ,// SDRAM Address
          .app_req_addr       (app_req_addr       ) ,// SDRAM Address

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