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`include "sdrc_define.v"
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`include "sdrc_define.v"
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module sdrc_top
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module sdrc_top
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(
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(
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sdr_width ,
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cfg_sdr_width ,
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cfg_colbits ,
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cfg_colbits ,
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// WB bus
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// WB bus
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wb_rst_i ,
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wb_rst_i ,
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wb_clk_i ,
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wb_clk_i ,
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//-----------------------------------------------
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//-----------------------------------------------
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// Global Variable
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// Global Variable
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// ----------------------------------------------
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// ----------------------------------------------
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input sdram_clk ; // SDRAM Clock
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input sdram_clk ; // SDRAM Clock
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input sdram_resetn ; // Reset Signal
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input sdram_resetn ; // Reset Signal
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input [1:0] sdr_width ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
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input [1:0] cfg_sdr_width ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
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input [1:0] cfg_colbits ; // 2'b00 - 8 Bit column address,
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input [1:0] cfg_colbits ; // 2'b00 - 8 Bit column address,
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// 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
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// 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
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//--------------------------------------
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//--------------------------------------
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// Wish Bone Interface
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// Wish Bone Interface
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sdrc_core #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_sdrc_core (
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sdrc_core #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_sdrc_core (
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.clk (sdram_clk ) ,
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.clk (sdram_clk ) ,
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.pad_clk (sdram_pad_clk ) ,
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.pad_clk (sdram_pad_clk ) ,
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.reset_n (sdram_resetn ) ,
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.reset_n (sdram_resetn ) ,
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.sdr_width (sdr_width ) ,
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.sdr_width (cfg_sdr_width ) ,
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.cfg_colbits (cfg_colbits ) ,
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.cfg_colbits (cfg_colbits ) ,
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/* Request from app */
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/* Request from app */
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.app_req (app_req ) ,// Transfer Request
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.app_req (app_req ) ,// Transfer Request
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.app_req_addr (app_req_addr ) ,// SDRAM Address
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.app_req_addr (app_req_addr ) ,// SDRAM Address
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