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Initial version with 16/32 Bit SDRAM Support
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Initial version with 16/32 Bit SDRAM Support
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: 0.1 - 24th Jan 2012
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: 0.1 - 24th Jan 2012
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8 Bit SDRAM Support is added
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8 Bit SDRAM Support is added
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0.2 - 31st Jan 2012
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0.2 - 31st Jan 2012
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sdram_dq and sdram_pad_clk are internally generated
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sdram_dq and sdram_pad_clk are internally generated
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0.3 - 26th April 2013
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Sdram Address witdh is increased from 12 to 13bits
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Copyright (C) 2000 Authors and OPENCORES.ORG
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Copyright (C) 2000 Authors and OPENCORES.ORG
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This source file may be used and distributed without
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This source file may be used and distributed without
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input wb_rst_i ;
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input wb_rst_i ;
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input wb_clk_i ;
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input wb_clk_i ;
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input wb_stb_i ;
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input wb_stb_i ;
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output wb_ack_o ;
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output wb_ack_o ;
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input [24:0] wb_addr_i ;
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input [APP_AW-1:0] wb_addr_i ;
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input wb_we_i ; // 1 - Write, 0 - Read
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input wb_we_i ; // 1 - Write, 0 - Read
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input [dw-1:0] wb_dat_i ;
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input [dw-1:0] wb_dat_i ;
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input [dw/8-1:0] wb_sel_i ; // Byte enable
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input [dw/8-1:0] wb_sel_i ; // Byte enable
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output [dw-1:0] wb_dat_o ;
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output [dw-1:0] wb_dat_o ;
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input wb_cyc_i ;
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input wb_cyc_i ;
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output sdr_ras_n ; // SDRAM ras
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output sdr_ras_n ; // SDRAM ras
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output sdr_cas_n ; // SDRAM cas
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output sdr_cas_n ; // SDRAM cas
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output sdr_we_n ; // SDRAM write enable
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output sdr_we_n ; // SDRAM write enable
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output [SDR_BW-1:0] sdr_dqm ; // SDRAM Data Mask
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output [SDR_BW-1:0] sdr_dqm ; // SDRAM Data Mask
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output [1:0] sdr_ba ; // SDRAM Bank Enable
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output [1:0] sdr_ba ; // SDRAM Bank Enable
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output [11:0] sdr_addr ; // SDRAM Address
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output [12:0] sdr_addr ; // SDRAM Address
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inout [SDR_DW-1:0] sdr_dq ; // SDRA Data Input/output
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inout [SDR_DW-1:0] sdr_dq ; // SDRA Data Input/output
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//------------------------------------------------
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//------------------------------------------------
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// Configuration Parameter
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// Configuration Parameter
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//------------------------------------------------
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//------------------------------------------------
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input [3:0] cfg_sdr_tras_d ; // Active to precharge delay
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input [3:0] cfg_sdr_tras_d ; // Active to precharge delay
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input [3:0] cfg_sdr_trp_d ; // Precharge to active delay
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input [3:0] cfg_sdr_trp_d ; // Precharge to active delay
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input [3:0] cfg_sdr_trcd_d ; // Active to R/W delay
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input [3:0] cfg_sdr_trcd_d ; // Active to R/W delay
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input cfg_sdr_en ; // Enable SDRAM controller
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input cfg_sdr_en ; // Enable SDRAM controller
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input [1:0] cfg_req_depth ; // Maximum Request accepted by SDRAM controller
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input [1:0] cfg_req_depth ; // Maximum Request accepted by SDRAM controller
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input [11:0] cfg_sdr_mode_reg ;
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input [12:0] cfg_sdr_mode_reg ;
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input [2:0] cfg_sdr_cas ; // SDRAM CAS Latency
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input [2:0] cfg_sdr_cas ; // SDRAM CAS Latency
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input [3:0] cfg_sdr_trcar_d ; // Auto-refresh period
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input [3:0] cfg_sdr_trcar_d ; // Auto-refresh period
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input [3:0] cfg_sdr_twr_d ; // Write recovery delay
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input [3:0] cfg_sdr_twr_d ; // Write recovery delay
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input [`SDR_RFSH_TIMER_W-1 : 0] cfg_sdr_rfsh;
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input [`SDR_RFSH_TIMER_W-1 : 0] cfg_sdr_rfsh;
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input [`SDR_RFSH_ROW_CNT_W -1 : 0] cfg_sdr_rfmax;
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input [`SDR_RFSH_ROW_CNT_W -1 : 0] cfg_sdr_rfmax;
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