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This file is part of the sdram controller project
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This file is part of the sdram controller project
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http://www.opencores.org/cores/sdr_ctrl/
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http://www.opencores.org/cores/sdr_ctrl/
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Description: WISHBONE to SDRAM Controller Bus Transalator
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Description: WISHBONE to SDRAM Controller Bus Transalator
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This module translate the WISHBONE protocol to custom sdram controller i/f
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1. This module translate the WISHBONE protocol to custom sdram controller i/f
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2. Also Handle the clock domain change from Application layer to Sdram layer
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To Do:
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To Do:
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nothing
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nothing
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Author(s): Dinesh Annayya, dinesha@opencores.org
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Author(s): Dinesh Annayya, dinesha@opencores.org
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Line 137... |
wire rddatafifo_full;
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wire rddatafifo_full;
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reg pending_read;
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reg pending_read;
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// Generate Address Enable only when internal fifo (Address + data are not full
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//-----------------------------------------------------------------------------
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// Ack Generaltion Logic
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// If Write Request - Acknowledge if the command and write FIFO are not full
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// If Read Request - Generate the Acknowledgment once read fifo has data
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// available
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//-----------------------------------------------------------------------------
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assign wb_ack_o = (wb_stb_i && wb_cyc_i && wb_we_i) ? // Write Phase
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assign wb_ack_o = (wb_stb_i && wb_cyc_i && wb_we_i) ? // Write Phase
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((!cmdfifo_full) && (!wrdatafifo_full)) :
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((!cmdfifo_full) && (!wrdatafifo_full)) :
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(wb_stb_i && wb_cyc_i && !wb_we_i) ? // Read Phase
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(wb_stb_i && wb_cyc_i && !wb_we_i) ? // Read Phase
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!rddatafifo_empty : 1'b0;
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!rddatafifo_empty : 1'b0;
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// Accept the cmdfifo only when burst start + address enable + address
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//---------------------------------------------------------------------------
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// valid is asserted
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// Command FIFO Write Generation
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wire cmdfifo_wr = (wb_stb_i && wb_cyc_i && wb_we_i) ? wb_ack_o :
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// If Write Request - Generate write, when Write fifo and command fifo is
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(wb_stb_i && wb_cyc_i && !wb_we_i) ? !pending_read: 1'b0 ;
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// not full
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// If Read Request - Generate write, when command fifo not full and there
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// is no pending read request.
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//---------------------------------------------------------------------------
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wire cmdfifo_wr = (wb_stb_i && wb_cyc_i && wb_we_i && (!cmdfifo_full) ) ? wb_ack_o :
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(wb_stb_i && wb_cyc_i && !wb_we_i && (!cmdfifo_full)) ? !pending_read: 1'b0 ;
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//---------------------------------------------------------------------------
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// command fifo read generation
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// Command FIFo read will be generated, whenever SDRAM Controller
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// Acknowldge the Request
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//----------------------------------------------------------------------------
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wire cmdfifo_rd = sdr_req_ack;
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wire cmdfifo_rd = sdr_req_ack;
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//---------------------------------------------------------------------------
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// Application layer request is generated towards the controller, whenever
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// Command FIFO is not full
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// --------------------------------------------------------------------------
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assign sdr_req = !cmdfifo_empty;
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assign sdr_req = !cmdfifo_empty;
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//----------------------------------------------------------------------------
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// Since Burst length is not known at the start of the Burst, It's assumed as
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// Single Cycle Burst. We need to improvise this ...
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// --------------------------------------------------------------------------
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wire [bl-1:0] burst_length = 1; // 0 Mean 1 Transfer
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wire [bl-1:0] burst_length = 1; // 0 Mean 1 Transfer
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//-----------------------------------------------------------------------------
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// In Wish Bone Spec, For Read Request has to be acked along with data.
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// We need to identify the pending read request.
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// Once we accept the read request, we should not accept one more read
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// request, untill we have transmitted the read data.
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// Pending Read will
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// set - with Read Request
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// reset - with Read Request + Ack
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// ----------------------------------------------------------------------------
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always @(posedge wb_rst_i or posedge wb_clk_i) begin
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always @(posedge wb_rst_i or posedge wb_clk_i) begin
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if(wb_rst_i) begin
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if(wb_rst_i) begin
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pending_read <= 1'b0;
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pending_read <= 1'b0;
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end else begin
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end else begin
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pending_read <= wb_stb_i & wb_cyc_i & !wb_we_i & !wb_ack_o;
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pending_read <= wb_stb_i & wb_cyc_i & !wb_we_i & !wb_ack_o;
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end
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end
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end
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end
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//---------------------------------------------------------------------
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// Async Command FIFO. This block handle the clock domain change from
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// Application layer to SDRAM Controller
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// ------------------------------------------------------------------
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// Address + Burst Length + W/R Request
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// Address + Burst Length + W/R Request
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async_fifo #(.W(30+bl+1),.DP(4)) u_cmdfifo (
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async_fifo #(.W(30+bl+1),.DP(4)) u_cmdfifo (
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// Write Path Sys CLock Domain
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// Write Path Sys CLock Domain
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.wr_clk (wb_clk_i),
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.wr_clk (wb_clk_i),
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.wr_reset_n (!wb_rst_i),
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.wr_reset_n (!wb_rst_i),
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Line 237... |
$display("ERROR:%m COMMAND FIFO READ OVERFLOW");
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$display("ERROR:%m COMMAND FIFO READ OVERFLOW");
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end
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end
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end
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end
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// synopsys translate_on
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// synopsys translate_on
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//---------------------------------------------------------------------
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// Write Data FIFO Write Generation, when ever Acked + Write Request
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// Note: Ack signal generation already taking account of FIFO full condition
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// ---------------------------------------------------------------------
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wire wrdatafifo_wr = wb_ack_o & wb_we_i ;
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wire wrdatafifo_wr = wb_ack_o & wb_we_i ;
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//------------------------------------------------------------------------
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// Write Data FIFO Read Generation, When ever Next Write request generated
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// from SDRAM Controller
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// ------------------------------------------------------------------------
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wire wrdatafifo_rd = sdr_wr_next;
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wire wrdatafifo_rd = sdr_wr_next;
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//------------------------------------------------------------------------
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// Async Write Data FIFO
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// This block handle the clock domain change over + Write Data + Byte mask
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// From Application layer to SDRAM controller layer
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//------------------------------------------------------------------------
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// Write DATA + Data Mask FIFO
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// Write DATA + Data Mask FIFO
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async_fifo #(.W(dw+(dw/8)), .DP(16)) u_wrdatafifo (
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async_fifo #(.W(dw+(dw/8)), .DP(16)) u_wrdatafifo (
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// Write Path , System clock domain
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// Write Path , System clock domain
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.wr_clk (wb_clk_i),
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.wr_clk (wb_clk_i),
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.wr_reset_n (!wb_rst_i),
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.wr_reset_n (!wb_rst_i),
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Line 296... |
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// -------------------------------------------------------------------
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// -------------------------------------------------------------------
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// READ DATA FIFO
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// READ DATA FIFO
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// ------------------------------------------------------------------
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// ------------------------------------------------------------------
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wire rd_eop; // last read indication
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wire rd_eop; // last read indication
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// Read FIFO write generation, when ever SDRAM controller issues the read
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// valid signal
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wire rddatafifo_wr = sdr_rd_valid;
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wire rddatafifo_wr = sdr_rd_valid;
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wire rddatafifo_rd = wb_ack_o & !wb_we_i & (rddatafifo_empty == 0);
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// READ DATA FIFO depth is kept small, assuming that Sys-CLock > SDRAM Clock
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// Read FIFO read generation, when ever ack is generated along with read
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// request.
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// Note: Ack generation is already accounted the write FIFO Not Empty
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// condition
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wire rddatafifo_rd = wb_ack_o & !wb_we_i;
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//-------------------------------------------------------------------------
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// Async Read FIFO
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// This block handles the clock domain change over + Read data from SDRAM
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// controller to Application layer.
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// Note:
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// 1. READ DATA FIFO depth is kept small, assuming that Sys-CLock > SDRAM Clock
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// READ DATA + EOP
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// READ DATA + EOP
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// 2. EOP indicate, last transfer of Burst Read Access. use-full for future
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// Tag handling per burst
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//
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// ------------------------------------------------------------------------
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async_fifo #(.W(dw+1), .DP(4)) u_rddatafifo (
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async_fifo #(.W(dw+1), .DP(4)) u_rddatafifo (
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// Write Path , SDRAM clock domain
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// Write Path , SDRAM clock domain
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.wr_clk (sdram_clk),
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.wr_clk (sdram_clk),
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.wr_reset_n (sdram_resetn),
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.wr_reset_n (sdram_resetn),
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.wr_en (rddatafifo_wr),
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.wr_en (rddatafifo_wr),
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