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Line 9... |
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To Do:
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To Do:
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nothing
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nothing
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Author(s): Dinesh Annayya, dinesha@opencores.org
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Author(s): Dinesh Annayya, dinesha@opencores.org
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Version : 0.0 - Initial Release
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0.1 - 2nd Feb 2012
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Async Fifo towards the application layer is selected with Registered Full Generation
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Copyright (C) 2000 Authors and OPENCORES.ORG
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Copyright (C) 2000 Authors and OPENCORES.ORG
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This source file may be used and distributed without
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This source file may be used and distributed without
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restriction provided that this copyright statement is not
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restriction provided that this copyright statement is not
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removed from the file and that any derivative work contains
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removed from the file and that any derivative work contains
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the original copyright notice and the associated disclaimer.
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the original copyright notice and the associated disclaimer.
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//---------------------------------------------------------------------
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//---------------------------------------------------------------------
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// Async Command FIFO. This block handle the clock domain change from
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// Async Command FIFO. This block handle the clock domain change from
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// Application layer to SDRAM Controller
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// Application layer to SDRAM Controller
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// ------------------------------------------------------------------
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// ------------------------------------------------------------------
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// Address + Burst Length + W/R Request
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// Address + Burst Length + W/R Request
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async_fifo #(.W(30+bl+1),.DP(4)) u_cmdfifo (
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async_fifo #(.W(30+bl+1),.DP(4),.WR_FAST(1'b0), .RD_FAST(1'b1)) u_cmdfifo (
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// Write Path Sys CLock Domain
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// Write Path Sys CLock Domain
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.wr_clk (wb_clk_i ),
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.wr_clk (wb_clk_i ),
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.wr_reset_n (!wb_rst_i ),
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.wr_reset_n (!wb_rst_i ),
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.wr_en (cmdfifo_wr ),
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.wr_en (cmdfifo_wr ),
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.wr_data ({burst_length,
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.wr_data ({burst_length,
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// This block handle the clock domain change over + Write Data + Byte mask
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// This block handle the clock domain change over + Write Data + Byte mask
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// From Application layer to SDRAM controller layer
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// From Application layer to SDRAM controller layer
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//------------------------------------------------------------------------
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//------------------------------------------------------------------------
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// Write DATA + Data Mask FIFO
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// Write DATA + Data Mask FIFO
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async_fifo #(.W(dw+(dw/8)), .DP(16)) u_wrdatafifo (
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async_fifo #(.W(dw+(dw/8)), .DP(8), .WR_FAST(1'b0), .RD_FAST(1'b1)) u_wrdatafifo (
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// Write Path , System clock domain
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// Write Path , System clock domain
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.wr_clk (wb_clk_i ),
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.wr_clk (wb_clk_i ),
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.wr_reset_n (!wb_rst_i ),
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.wr_reset_n (!wb_rst_i ),
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.wr_en (wrdatafifo_wr ),
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.wr_en (wrdatafifo_wr ),
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.wr_data ({~wb_sel_i,
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.wr_data ({~wb_sel_i,
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// READ DATA + EOP
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// READ DATA + EOP
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// 2. EOP indicate, last transfer of Burst Read Access. use-full for future
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// 2. EOP indicate, last transfer of Burst Read Access. use-full for future
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// Tag handling per burst
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// Tag handling per burst
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//
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//
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// ------------------------------------------------------------------------
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// ------------------------------------------------------------------------
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async_fifo #(.W(dw+1), .DP(4)) u_rddatafifo (
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async_fifo #(.W(dw+1), .DP(4), .WR_FAST(1'b0), .RD_FAST(1'b1) ) u_rddatafifo (
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// Write Path , SDRAM clock domain
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// Write Path , SDRAM clock domain
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.wr_clk (sdram_clk ),
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.wr_clk (sdram_clk ),
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.wr_reset_n (sdram_resetn ),
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.wr_reset_n (sdram_resetn ),
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.wr_en (rddatafifo_wr ),
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.wr_en (rddatafifo_wr ),
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.wr_data ({sdr_last_rd,
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.wr_data ({sdr_last_rd,
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