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[/] [sdr_ctrl/] [trunk/] [verif/] [log/] [core_sdr16_sim.log] - Diff between revs 27 and 28

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Rev 27 Rev 28
Line 290... Line 290...
# READ STATUS: Burst-No:           3 Addr: 03d2727d Rxd: 44556677
# READ STATUS: Burst-No:           3 Addr: 03d2727d Rxd: 44556677
# READ STATUS: Burst-No:           4 Addr: 03d2727f Rxd: 55667788
# READ STATUS: Burst-No:           4 Addr: 03d2727f Rxd: 55667788
###############################
###############################
# STATUS: SDRAM Write/Read TEST PASSED
# STATUS: SDRAM Write/Read TEST PASSED
###############################
###############################
# ** Note: $finish    : ../tb/tb_core.sv(298)
# ** Note: $finish    : ../tb/tb_core.sv(300)
#    Time: 53060 ns  Iteration: 0  Instance: /tb_core
#    Time: 53060 ns  Iteration: 0  Instance: /tb_core
### test 1: basic_test1 --> PASSED
### test 1: basic_test1 --> PASSED
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