| Line 23... |
Line 23... |
# Loading work.sdrc_bank_ctl
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# Loading work.sdrc_bank_ctl
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# Loading work.sdrc_bank_fsm
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# Loading work.sdrc_bank_fsm
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# Loading work.sdrc_xfr_ctl
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# Loading work.sdrc_xfr_ctl
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# Loading work.sdrc_bs_convert
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# Loading work.sdrc_bs_convert
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# Loading work.mt48lc2m32b2
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# Loading work.mt48lc2m32b2
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# ** Warning: (vsim-3015) ../tb/tb_top.sv(199): [PCDPC] - Port size (11 or 11) does not match connection size (12) for port 'Addr'. The port definition is at: ../model/mt48lc2m32b2.v(42).
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# ** Warning: (vsim-3015) ../tb/tb_top.sv(182): [PCDPC] - Port size (11 or 11) does not match connection size (12) for port 'Addr'. The port definition is at: ../model/mt48lc2m32b2.v(42).
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# Region: /tb_top/u_sdram32
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# Region: /tb_top/u_sdram32
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# do run.do
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# do run.do
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# tb_top.u_sdram32 : at time 10212.0 ns AREF : Auto Refresh
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# tb_top.u_sdram32 : at time 10212.0 ns AREF : Auto Refresh
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# tb_top.u_sdram32 : at time 10392.0 ns AREF : Auto Refresh
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# tb_top.u_sdram32 : at time 10392.0 ns AREF : Auto Refresh
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# tb_top.u_sdram32 : at time 10572.0 ns AREF : Auto Refresh
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# tb_top.u_sdram32 : at time 10572.0 ns AREF : Auto Refresh
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| Line 731... |
Line 731... |
# tb_top.u_sdram32 : at time 61178.0 ns READ : Bank = 0 Row = 1319, Col = 161, Data = 55667788
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# tb_top.u_sdram32 : at time 61178.0 ns READ : Bank = 0 Row = 1319, Col = 161, Data = 55667788
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# READ STATUS: Burst-No: 4 Addr: 00f49ca1 Rxd: 55667788
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# READ STATUS: Burst-No: 4 Addr: 00f49ca1 Rxd: 55667788
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###############################
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###############################
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# STATUS: SDRAM Write/Read TEST PASSED
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# STATUS: SDRAM Write/Read TEST PASSED
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###############################
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###############################
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# ** Note: $finish : ../tb/tb_top.sv(304)
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# ** Note: $finish : ../tb/tb_top.sv(283)
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# Time: 71260 ns Iteration: 0 Instance: /tb_top
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# Time: 71260 ns Iteration: 0 Instance: /tb_top
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