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[/] [sdr_ctrl/] [trunk/] [verif/] [log/] [top_SDR_8BIT_basic_test1.log] - Diff between revs 28 and 37

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Rev 28 Rev 37
Line 1436... Line 1436...
# at time     67778 ns READ : Bank = 2 Row = 1180, Col = 135, Data = 55, Dqm = 0
# at time     67778 ns READ : Bank = 2 Row = 1180, Col = 135, Data = 55, Dqm = 0
# READ STATUS: Burst-No:           4 Addr: 00f49ca1 Rxd: 55667788
# READ STATUS: Burst-No:           4 Addr: 00f49ca1 Rxd: 55667788
###############################
###############################
# STATUS: SDRAM Write/Read TEST PASSED
# STATUS: SDRAM Write/Read TEST PASSED
###############################
###############################
# ** Note: $finish    : ../tb/tb_top.sv(304)
# ** Note: $finish    : ../tb/tb_top.sv(283)
#    Time: 77860 ns  Iteration: 0  Instance: /tb_top
#    Time: 77860 ns  Iteration: 0  Instance: /tb_top

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