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[/] [sdr_ctrl/] [trunk/] [verif/] [log/] [top_SDR_8BIT_basic_test1.log] - Diff between revs 28 and 37
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Rev 37 |
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# at time 67778 ns READ : Bank = 2 Row = 1180, Col = 135, Data = 55, Dqm = 0
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# at time 67778 ns READ : Bank = 2 Row = 1180, Col = 135, Data = 55, Dqm = 0
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# READ STATUS: Burst-No: 4 Addr: 00f49ca1 Rxd: 55667788
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# READ STATUS: Burst-No: 4 Addr: 00f49ca1 Rxd: 55667788
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###############################
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###############################
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# STATUS: SDRAM Write/Read TEST PASSED
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# STATUS: SDRAM Write/Read TEST PASSED
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###############################
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###############################
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# ** Note: $finish : ../tb/tb_top.sv(304)
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# ** Note: $finish : ../tb/tb_top.sv(283)
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# Time: 77860 ns Iteration: 0 Instance: /tb_top
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# Time: 77860 ns Iteration: 0 Instance: /tb_top
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