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[/] [sdr_ctrl/] [trunk/] [verif/] [log/] [top_SDR_8BIT_complie.log] - Diff between revs 65 and 73

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Rev 65 Rev 73
** Note: (vlog-1901) OptionFile "C:/cygwin/home/Dinesh/projects/sdr_ctrl/sdr_ctrl/trunk/verif/run/vlog.opt" not found. Ignored.
Model Technology ModelSim Microsemi vlog 2020.3 Compiler 2020.07 Jul 13 2020
Model Technology ModelSim ACTEL vlog 6.6d Compiler 2010.11 Nov  2 2010
Start time: 18:52:56 on Aug 27,2021
 
vlog -work work "+define+SDR_8BIT" -f filelist_top.f
-- Compiling module tb_top
-- Compiling module tb_top
-- Compiling module IS42VM16400K
-- Compiling module IS42VM16400K
-- Compiling module mt48lc2m32b2
-- Compiling module mt48lc2m32b2
-- Compiling module mt48lc8m8a2
-- Compiling module mt48lc8m8a2
-- Compiling module sdrc_top
-- Compiling module sdrc_top
-- Compiling module wb2sdrc
-- Compiling module wb2sdrc
-- Compiling module async_fifo
-- Compiling module async_fifo
-- Compiling module sdrc_core
-- Compiling module sdrc_core
-- Compiling module sdrc_bank_ctl
-- Compiling module sdrc_bank_ctl
-- Compiling module sdrc_bank_fsm
-- Compiling module sdrc_bank_fsm
-- Compiling module sdrc_bs_convert
-- Compiling module sdrc_bs_convert
-- Compiling module sdrc_req_gen
-- Compiling module sdrc_req_gen
-- Compiling module sdrc_xfr_ctl
-- Compiling module sdrc_xfr_ctl
Top level modules:
Top level modules:
        tb_top
        tb_top
        IS42VM16400K
        IS42VM16400K
        mt48lc2m32b2
        mt48lc2m32b2
 
End time: 18:52:56 on Aug 27,2021, Elapsed time: 0:00:00
 
Errors: 0, Warnings: 0
 
 

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