** Note: (vlog-1901) OptionFile "C:/cygwin/home/Dinesh/projects/sdr_ctrl/sdr_ctrl/trunk/verif/run/vlog.opt" not found. Ignored.
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Model Technology ModelSim Microsemi vlog 2020.3 Compiler 2020.07 Jul 13 2020
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Model Technology ModelSim ACTEL vlog 6.6d Compiler 2010.11 Nov 2 2010
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Start time: 18:52:56 on Aug 27,2021
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vlog -work work "+define+SDR_8BIT" -f filelist_top.f
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-- Compiling module tb_top
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-- Compiling module tb_top
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-- Compiling module IS42VM16400K
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-- Compiling module IS42VM16400K
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-- Compiling module mt48lc2m32b2
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-- Compiling module mt48lc2m32b2
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-- Compiling module mt48lc8m8a2
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-- Compiling module mt48lc8m8a2
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-- Compiling module sdrc_top
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-- Compiling module sdrc_top
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-- Compiling module wb2sdrc
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-- Compiling module wb2sdrc
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-- Compiling module async_fifo
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-- Compiling module async_fifo
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-- Compiling module sdrc_core
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-- Compiling module sdrc_core
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-- Compiling module sdrc_bank_ctl
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-- Compiling module sdrc_bank_ctl
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-- Compiling module sdrc_bank_fsm
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-- Compiling module sdrc_bank_fsm
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-- Compiling module sdrc_bs_convert
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-- Compiling module sdrc_bs_convert
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-- Compiling module sdrc_req_gen
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-- Compiling module sdrc_req_gen
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-- Compiling module sdrc_xfr_ctl
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-- Compiling module sdrc_xfr_ctl
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Top level modules:
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Top level modules:
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tb_top
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tb_top
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IS42VM16400K
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IS42VM16400K
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mt48lc2m32b2
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mt48lc2m32b2
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End time: 18:52:56 on Aug 27,2021, Elapsed time: 0:00:00
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Errors: 0, Warnings: 0
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