OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [model/] [mt48lc8m8a2.v] - Diff between revs 17 and 32

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 17 Rev 32
Line 113... Line 113...
 
 
    // CAS Latency Decode
    // CAS Latency Decode
    wire      Cas_latency_2    = ~Mode_reg[6] &  Mode_reg[5] & ~Mode_reg[4];
    wire      Cas_latency_2    = ~Mode_reg[6] &  Mode_reg[5] & ~Mode_reg[4];
    wire      Cas_latency_3    = ~Mode_reg[6] &  Mode_reg[5] &  Mode_reg[4];
    wire      Cas_latency_3    = ~Mode_reg[6] &  Mode_reg[5] &  Mode_reg[4];
 
 
 
`ifdef VERBOSE
 
    wire      Debug            = 1'b1;                          // Debug messages : 1 = On
 
`else
 
    wire      Debug            = 1'b0;                          // Debug messages : 1 = On
 
`endif
    // Write Burst Mode
    // Write Burst Mode
    wire      Write_burst_mode = Mode_reg[9];
    wire      Write_burst_mode = Mode_reg[9];
 
 
    reg       Debug;                         // Debug messages : 1 = On
 
    wire      Dq_chk           = Sys_clk & Data_in_enable;      // Check setup/hold time for DQ
    wire      Dq_chk           = Sys_clk & Data_in_enable;      // Check setup/hold time for DQ
 
 
    assign    Dq               = Dq_reg;                        // DQ buffer
    assign    Dq               = Dq_reg;                        // DQ buffer
 
 
    // Commands Operation
    // Commands Operation
Line 156... Line 160...
    time      RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
    time      RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
    time      RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
    time      RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
    time      RP_chk0, RP_chk1, RP_chk2, RP_chk3;
    time      RP_chk0, RP_chk1, RP_chk2, RP_chk3;
 
 
    initial begin
    initial begin
       Debug = 1'b0;
 
 
 
        Dq_reg = {data_bits{1'bz}};
        Dq_reg = {data_bits{1'bz}};
        {Data_in_enable, Data_out_enable} = 0;
        {Data_in_enable, Data_out_enable} = 0;
        {Act_b0, Act_b1, Act_b2, Act_b3} = 4'b0000;
        {Act_b0, Act_b1, Act_b2, Act_b3} = 4'b0000;
        {Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b0000;
        {Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b0000;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.