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[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] [tb_core.sv] - Diff between revs 30 and 43

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Rev 30 Rev 43
Line 7... Line 7...
////  Description                                                 ////
////  Description                                                 ////
////  SDRAM CTRL definitions.                                     ////
////  SDRAM CTRL definitions.                                     ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////    nothing                                                   ////
////    nothing                                                   ////
 
//   Version  :0.1 - Test Bench automation is improvised with     ////
 
//             seperate data,address,burst length fifo.           ////
 
//             Now user can create different write and            ////
 
//             read sequence                                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
Line 228... Line 232...
          .Dqm                (sdr_dqm            )
          .Dqm                (sdr_dqm            )
     );
     );
`endif
`endif
 
 
//--------------------
//--------------------
// Write/Read Burst FIFO
// data/address/burst length FIFO
//--------------------
//--------------------
int wrdfifo[$]; // write data fifo
int dfifo[$]; // data fifo
int rddfifo[$]; // read data fifo
int afifo[$]; // address  fifo
 
int bfifo[$]; // Burst Length fifo
 
 
reg [31:0] read_data;
reg [31:0] read_data;
reg [31:0] ErrCnt;
reg [31:0] ErrCnt;
int k;
int k;
reg [31:0] StartAddr;
reg [31:0] StartAddr;
Line 263... Line 268...
  #1000;
  #1000;
  wait(u_dut.sdr_init_done == 1);
  wait(u_dut.sdr_init_done == 1);
 
 
  #1000;
  #1000;
 
 
  wrdfifo.push_back(32'h11223344);
  burst_write(32'h4_0000,6'h4);
  wrdfifo.push_back(32'h22334455);
 
  wrdfifo.push_back(32'h33445566);
 
  wrdfifo.push_back(32'h44556677);
 
  wrdfifo.push_back(32'h55667788);
 
 
 
  burst_write(32'h40000);
 
 #1000;
 #1000;
  burst_read(32'h40000);
  burst_read();
 
 
 #1000;
 #1000;
  burst_write(32'h7000_0000);
  burst_write(32'h0040_0000,6'h5);
 #1000;
 #1000;
  burst_read(32'h7000_0000);
  burst_read();
 
 
 
  // 4 Write & 4 Read
 
  burst_write(32'h4_0000,6'h4);
 
  burst_write(32'h5_0000,6'h5);
 
  burst_write(32'h6_0000,6'h6);
 
  burst_write(32'h7_0000,6'h7);
 
  burst_read();
 
  burst_read();
 
  burst_read();
 
  burst_read();
 
 
 
 
 
  // 2 write and 2 read random
 
 
  for(k=0; k < 20; k++) begin
  for(k=0; k < 20; k++) begin
     StartAddr = $random & 32'h07FFFFFF;
     StartAddr = $random & 32'h003FFFFF;
     burst_write(StartAddr);
     burst_write(StartAddr,($random & 8'h3f)+1);
    #1000;
 #100;
     burst_read(StartAddr);
 
 
     StartAddr = $random & 32'h003FFFFF;
 
     burst_write(StartAddr,($random & 8'h3f)+1);
 
 #100;
 
     burst_read();
 
 #100;
 
     burst_read();
 
 #100;
  end
  end
 
 
 
 
 
 
  #10000;
  #10000;
 
 
        $display("###############################");
        $display("###############################");
    if(ErrCnt == 0)
    if(ErrCnt == 0)
        $display("STATUS: SDRAM Write/Read TEST PASSED");
        $display("STATUS: SDRAM Write/Read TEST PASSED");
Line 298... Line 318...
        $display("###############################");
        $display("###############################");
 
 
    $finish;
    $finish;
end
end
 
 
 
 
task burst_write;
task burst_write;
input [31:0] Address;
input [31:0] Address;
 
input [7:0]  bl;
int i;
int i;
begin
begin
 
  afifo.push_back(Address);
 
  bfifo.push_back(bl);
 
 
   @ (negedge sdram_clk);
   @ (negedge sdram_clk);
   app_req        = 1;
   app_req        = 1;
   app_wr_en_n    = 0;
   app_wr_en_n    = 0;
   app_req_wr_n   = 1'b0;
   app_req_wr_n   = 1'b0;
   $display("Write Address: %x, Burst Size: %d",Address,wrdfifo.size);
 
   app_req_addr  = Address[31:2];
   app_req_addr  = Address[31:2];
   app_req_len    = wrdfifo.size;
   app_req_len    = bl;
 
   $display("Write Address: %x, Burst Size: %d",Address,bl);
 
 
   // wait for app_req_ack == 1
   // wait for app_req_ack == 1
   do begin
   do begin
       @ (posedge sdram_clk);
       @ (posedge sdram_clk);
   end while(app_req_ack == 1'b0);
   end while(app_req_ack == 1'b0);
   @ (negedge sdram_clk);
   @ (negedge sdram_clk);
   app_req           = 0;
   app_req           = 0;
 
 
   for(i=0; i < wrdfifo.size; i++) begin
   for(i=0; i < bl; i++) begin
      app_wr_data     = wrdfifo[i];
      app_wr_data        = $random & 32'hFFFFFFFF;
 
      dfifo.push_back(app_wr_data);
 
 
      do begin
      do begin
          @ (posedge sdram_clk);
          @ (posedge sdram_clk);
      end while(app_wr_next_req == 1'b0);
      end while(app_wr_next_req == 1'b0);
          @ (negedge sdram_clk);
          @ (negedge sdram_clk);
 
 
       $display("Status: Burst-No: %d  Write Address: %x  WriteData: %x ",i,Address,app_wr_data);
       $display("Status: Burst-No: %d  Write Address: %x  WriteData: %x ",i,Address,app_wr_data);
   end
   end
   app_req           = 0;
   app_req           = 0;
   app_wr_en_n       = 4'hF;
   app_wr_en_n       = 4'hF;
 
 
 
 
end
end
endtask
endtask
 
 
task burst_read;
task burst_read;
input [31:0] Address;
reg [31:0] Address;
 
reg [7:0]  bl;
 
 
int i,j;
int i,j;
reg [31:0]   rd_data;
reg [31:0]   exp_data;
begin
begin
   @ (negedge sdram_clk);
 
 
   Address = afifo.pop_front();
 
   bl      = bfifo.pop_front();
 
 
      app_req        = 1;
      app_req        = 1;
      app_wr_en_n    = 0;
      app_wr_en_n    = 0;
      app_req_wr_n   = 1;
      app_req_wr_n   = 1;
      app_req_addr   = Address[29:2];
      app_req_addr   = Address[29:2];
      app_req_len    = wrdfifo.size;
   app_req_len    = bl;
 
 
      // wait for app_req_ack == 1
      // wait for app_req_ack == 1
      do begin
      do begin
          @ (posedge sdram_clk);
          @ (posedge sdram_clk);
      end while(app_req_ack == 1'b0);
      end while(app_req_ack == 1'b0);
      @ (negedge sdram_clk);
      @ (negedge sdram_clk);
      app_req           = 0;
      app_req           = 0;
 
 
      for(j=0; j < wrdfifo.size; j++) begin
      for(j=0; j < bl; j++) begin
         wait(app_rd_valid == 1);
         wait(app_rd_valid == 1);
         if(app_rd_data !== wrdfifo[j]) begin
         exp_data        = dfifo.pop_front(); // Exptected Read Data
             $display("READ ERROR: Burst-No: %d Addr: %x Rxp: %x Exd: %x",j,Address+(j*2),app_rd_data,wrdfifo[j]);
         if(app_rd_data !== exp_data) begin
 
             $display("READ ERROR: Burst-No: %d Addr: %x Rxp: %x Exd: %x",j,Address+(j*2),app_rd_data,exp_data);
             ErrCnt = ErrCnt+1;
             ErrCnt = ErrCnt+1;
         end else begin
         end else begin
             $display("READ STATUS: Burst-No: %d Addr: %x Rxd: %x",j,Address+(j*2),app_rd_data);
             $display("READ STATUS: Burst-No: %d Addr: %x Rxd: %x",j,Address+(j*2),app_rd_data);
         end
         end
         @ (posedge sdram_clk);
         @ (posedge sdram_clk);

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