| Line 68... |
Line 68... |
// Application Interface bus
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// Application Interface bus
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//-------------------------------------------
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//-------------------------------------------
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reg app_req ; // Application Request
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reg app_req ; // Application Request
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reg [8:0] app_req_len ; // Burst Request length
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reg [8:0] app_req_len ; // Burst Request length
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wire app_req_ack ; // Application Request Ack
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wire app_req_ack ; // Application Request Ack
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reg [29:0] app_req_addr ; // Application Address
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reg [24:0] app_req_addr ; // Application Address
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reg app_req_wr_n ; // 1 -> Read, 0 -> Write
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reg app_req_wr_n ; // 1 -> Read, 0 -> Write
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reg [dw-1:0] app_wr_data ; // Write Data
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reg [dw-1:0] app_wr_data ; // Write Data
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reg [dw/8-1:0] app_wr_en_n ; // Write Enable, Active Low
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reg [dw/8-1:0] app_wr_en_n ; // Write Enable, Active Low
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wire app_rd_valid ; // Read Valid
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wire app_rd_valid ; // Read Valid
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wire app_last_rd ; // Last Read Valid
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wire app_last_rd ; // Last Read Valid
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| Line 476... |
Line 476... |
@ (negedge sdram_clk);
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@ (negedge sdram_clk);
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$display("Status: Burst-No: %d Write Address: %x WriteData: %x ",i,Address,app_wr_data);
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$display("Status: Burst-No: %d Write Address: %x WriteData: %x ",i,Address,app_wr_data);
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end
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end
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app_req = 0;
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app_req = 0;
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app_wr_en_n = 4'hF;
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app_wr_en_n = 'hx;
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app_req_wr_n = 'hx;
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app_req_addr = 'hx;
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app_req_len = 'hx;
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end
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end
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endtask
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endtask
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| Line 493... |
Line 496... |
begin
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begin
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Address = afifo.pop_front();
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Address = afifo.pop_front();
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bl = bfifo.pop_front();
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bl = bfifo.pop_front();
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@ (negedge sdram_clk);
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app_req = 1;
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app_req = 1;
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app_wr_en_n = 0;
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app_wr_en_n = 0;
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app_req_wr_n = 1;
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app_req_wr_n = 1;
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app_req_addr = Address[29:2];
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app_req_addr = Address[29:2];
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app_req_len = bl;
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app_req_len = bl;
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| Line 505... |
Line 509... |
do begin
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do begin
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@ (posedge sdram_clk);
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@ (posedge sdram_clk);
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end while(app_req_ack == 1'b0);
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end while(app_req_ack == 1'b0);
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@ (negedge sdram_clk);
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@ (negedge sdram_clk);
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app_req = 0;
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app_req = 0;
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app_wr_en_n = 'hx;
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app_req_wr_n = 'hx;
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app_req_addr = 'hx;
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app_req_len = 'hx;
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for(j=0; j < bl; j++) begin
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for(j=0; j < bl; j++) begin
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wait(app_rd_valid == 1);
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wait(app_rd_valid == 1);
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exp_data = dfifo.pop_front(); // Exptected Read Data
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exp_data = dfifo.pop_front(); // Exptected Read Data
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if(app_rd_data !== exp_data) begin
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if(app_rd_data !== exp_data) begin
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