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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// This file is part of the SDRAM Controller project ////
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//// http://www.opencores.org/cores/sdr_ctrl/ ////
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//// ////
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//// Description ////
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//// SDRAM CTRL definitions. ////
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//// ////
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//// To Do: ////
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//// nothing ////
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//// ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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`timescale 1ns/1ps
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// This testbench verify with SDRAM TOP
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module tb_top;
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parameter P_SYS = 10; // 100MHz
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// General
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reg RESETN;
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reg sdram_clk;
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initial sdram_clk = 0;
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always #(P_SYS/2) sdram_clk = !sdram_clk;
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parameter dw = 32; // data width
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parameter tw = 8; // tag id width
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parameter bl = 5; // burst_lenght_width
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//-------------------------------------------
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// Application Interface bus
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//-------------------------------------------
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reg app_req ; // Application Request
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reg [8:0] app_req_len ; // Burst Request length
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wire app_req_ack ; // Application Request Ack
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reg [29:0] app_req_addr ; // Application Address
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reg app_req_wr_n ; // 1 -> Read, 0 -> Write
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reg [dw-1:0] app_wr_data ; // Write Data
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reg [dw/8-1:0] app_wr_en_n ; // Write Enable, Active Low
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wire app_rd_valid ; // Read Valid
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wire [dw-1:0] app_rd_data ; // Read Data
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//--------------------------------------------
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// SDRAM I/F
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//--------------------------------------------
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`ifdef SDR_32BIT
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wire [31:0] Dq ; // SDRAM Read/Write Data Bus
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wire [31:0] sdr_dout ; // SDRAM Data Out
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wire [31:0] pad_sdr_din ; // SDRAM Data Input
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wire [3:0] sdr_den_n ; // SDRAM Data Enable
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wire [3:0] sdr_dqm ; // SDRAM DATA Mask
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`elsif SDR_16BIT
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wire [15:0] Dq ; // SDRAM Read/Write Data Bus
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wire [15:0] sdr_dout ; // SDRAM Data Out
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wire [15:0] pad_sdr_din ; // SDRAM Data Input
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wire [1:0] sdr_den_n ; // SDRAM Data Enable
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wire [1:0] sdr_dqm ; // SDRAM DATA Mask
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`else
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wire [7:0] Dq ; // SDRAM Read/Write Data Bus
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wire [7:0] sdr_dout ; // SDRAM Data Out
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wire [7:0] pad_sdr_din ; // SDRAM Data Input
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wire [0:0] sdr_den_n ; // SDRAM Data Enable
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wire [0:0] sdr_dqm ; // SDRAM DATA Mask
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`endif
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wire [1:0] sdr_ba ; // SDRAM Bank Select
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wire [11:0] sdr_addr ; // SDRAM ADRESS
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wire sdr_init_done ; // SDRAM Init Done
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// to fix the sdram interface timing issue
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wire #(2.0) sdram_clk_d = sdram_clk;
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wire #(1.0) pad_clk = sdram_clk_d;
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`ifdef SDR_32BIT
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sdrc_core #(.SDR_DW(32),.SDR_BW(4)) u_dut(
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`elsif SDR_16BIT
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sdrc_core #(.SDR_DW(16),.SDR_BW(2)) u_dut(
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`else // 8 BIT SDRAM
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sdrc_core #(.SDR_DW(8),.SDR_BW(1)) u_dut(
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`endif
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// System
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.clk (sdram_clk ),
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.reset_n (RESETN ),
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.pad_clk (pad_clk ),
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`ifdef SDR_32BIT
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.sdr_width (2'b00 ), // 32 BIT SDRAM
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`elsif SDR_16BIT
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.sdr_width (2'b01 ), // 16 BIT SDRAM
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`else
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.sdr_width (2'b10 ), // 8 BIT SDRAM
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`endif
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.cfg_colbits (2'b00 ), // 8 Bit Column Address
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/* Request from app */
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.app_req (app_req ), // Transfer Request
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.app_req_addr (app_req_addr ), // SDRAM Address
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.app_req_addr_mask (29'h1FFF_FFFF ), // Address mask for queue wrap
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.app_req_len (app_req_len ), // Burst Length (in 16 bit words)
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.app_req_wrap (1'b0 ), // Wrap mode request (xfr_len = 4)
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.app_req_wr_n (app_req_wr_n ), // 0 => Write request, 1 => read req
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.app_req_ack (app_req_ack ), // Request has been accepted
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.sdr_core_busy_n ( ), // OK to arbitrate next request
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.app_wr_data (app_wr_data ),
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.app_wr_en_n (app_wr_en_n ),
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.app_rd_data (app_rd_data ),
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.app_rd_valid (app_rd_valid ),
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.app_wr_next_req (app_wr_next_req ),
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.app_req_dma_last (app_req ),
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/* Interface to SDRAMs */
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.sdr_cs_n (sdr_cs_n ),
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.sdr_cke (sdr_cke ),
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.sdr_ras_n (sdr_ras_n ),
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.sdr_cas_n (sdr_cas_n ),
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.sdr_we_n (sdr_we_n ),
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.sdr_dqm (sdr_dqm ),
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.sdr_ba (sdr_ba ),
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.sdr_addr (sdr_addr ),
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.pad_sdr_din (Dq ),
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.sdr_dout (sdr_dout ),
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.sdr_den_n (sdr_den_n ),
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/* Parameters */
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.sdr_init_done (sdr_init_done ),
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.cfg_req_depth (2'h2 ), //how many req. buffer should hold
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.cfg_sdr_en (1'b1 ),
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.cfg_sdr_mode_reg (12'h033 ),
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.cfg_sdr_tras_d (4'h4 ),
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.cfg_sdr_trp_d (4'h2 ),
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.cfg_sdr_trcd_d (4'h2 ),
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.cfg_sdr_cas (3'h3 ),
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.cfg_sdr_trcar_d (4'h7 ),
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.cfg_sdr_twr_d (4'h1 ),
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.cfg_sdr_rfsh (12'hC35 ),
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.cfg_sdr_rfmax (3'h6 )
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);
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`ifdef SDR_32BIT
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assign Dq[7:0] = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0] : 8'hZZ;
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assign Dq[15:8] = (sdr_den_n[1] == 1'b0) ? sdr_dout[15:8] : 8'hZZ;
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assign Dq[23:16] = (sdr_den_n[2] == 1'b0) ? sdr_dout[23:16] : 8'hZZ;
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assign Dq[31:24] = (sdr_den_n[3] == 1'b0) ? sdr_dout[31:24] : 8'hZZ;
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mt48lc2m32b2 #(.data_bits(32)) u_sdram32 (
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.Dq (Dq ) ,
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.Addr (sdr_addr ),
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.Ba (sdr_ba ),
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.Clk (sdram_clk_d ),
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.Cke (sdr_cke ),
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.Cs_n (sdr_cs_n ),
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.Ras_n (sdr_ras_n ),
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.Cas_n (sdr_cas_n ),
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.We_n (sdr_we_n ),
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.Dqm (sdr_dqm )
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);
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`elsif SDR_16BIT
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assign Dq[7:0] = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0] : 8'hZZ;
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assign Dq[15:8] = (sdr_den_n[1] == 1'b0) ? sdr_dout[15:8] : 8'hZZ;
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IS42VM16400K u_sdram16 (
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.dq (Dq ),
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.addr (sdr_addr ),
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.ba (sdr_ba ),
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.clk (sdram_clk_d ),
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.cke (sdr_cke ),
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.csb (sdr_cs_n ),
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.rasb (sdr_ras_n ),
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.casb (sdr_cas_n ),
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.web (sdr_we_n ),
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.dqm (sdr_dqm )
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);
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`else
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assign Dq[7:0] = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0] : 8'hZZ;
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mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (
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.Dq (Dq ) ,
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.Addr (sdr_addr ),
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.Ba (sdr_ba ),
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.Clk (sdram_clk_d ),
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.Cke (sdr_cke ),
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.Cs_n (sdr_cs_n ),
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.Ras_n (sdr_ras_n ),
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.Cas_n (sdr_cas_n ),
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.We_n (sdr_we_n ),
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.Dqm (sdr_dqm )
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);
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`endif
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//--------------------
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// Write/Read Burst FIFO
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//--------------------
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int wrdfifo[$]; // write data fifo
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int rddfifo[$]; // read data fifo
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reg [31:0] read_data;
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reg [31:0] ErrCnt;
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int k;
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reg [31:0] StartAddr;
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/////////////////////////////////////////////////////////////////////////
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// Test Case
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/////////////////////////////////////////////////////////////////////////
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initial begin //{
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ErrCnt = 0;
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app_req_addr = 0;
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app_wr_data = 0;
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app_wr_en_n = 4'hF;
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app_req_wr_n = 0;
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app_req = 0;
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app_req_len = 0;
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RESETN = 1'h1;
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#100
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// Applying reset
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RESETN = 1'h0;
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#10000;
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// Releasing reset
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RESETN = 1'h1;
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#1000;
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wait(u_dut.sdr_init_done == 1);
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#1000;
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wrdfifo.push_back(32'h11223344);
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wrdfifo.push_back(32'h22334455);
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wrdfifo.push_back(32'h33445566);
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wrdfifo.push_back(32'h44556677);
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wrdfifo.push_back(32'h55667788);
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burst_write(32'h40000);
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#1000;
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burst_read(32'h40000);
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#1000;
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burst_write(32'h7000_0000);
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#1000;
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burst_read(32'h7000_0000);
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for(k=0; k < 20; k++) begin
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StartAddr = $random & 32'h07FFFFFF;
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burst_write(StartAddr);
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#1000;
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burst_read(StartAddr);
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end
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#10000;
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$display("###############################");
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if(ErrCnt == 0)
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$display("STATUS: SDRAM Write/Read TEST PASSED");
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else
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$display("ERROR: SDRAM Write/Read TEST FAILED");
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$display("###############################");
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$finish;
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end
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task burst_write;
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input [31:0] Address;
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int i;
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begin
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@ (negedge sdram_clk);
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app_req = 1;
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app_wr_en_n = 0;
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app_req_wr_n = 1'b0;
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$display("Write Address: %x, Burst Size: %d",Address,wrdfifo.size);
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app_req_addr = Address[31:2];
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app_req_len = wrdfifo.size;
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// wait for app_req_ack == 1
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do begin
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@ (posedge sdram_clk);
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end while(app_req_ack == 1'b0);
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@ (negedge sdram_clk);
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app_req = 0;
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for(i=0; i < wrdfifo.size; i++) begin
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app_wr_data = wrdfifo[i];
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do begin
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@ (posedge sdram_clk);
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end while(app_wr_next_req == 1'b0);
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@ (negedge sdram_clk);
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$display("Status: Burst-No: %d Write Address: %x WriteData: %x ",i,Address,app_wr_data);
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end
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app_req = 0;
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app_wr_en_n = 4'hF;
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end
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endtask
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task burst_read;
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input [31:0] Address;
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int i,j;
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reg [31:0] rd_data;
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begin
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@ (negedge sdram_clk);
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app_req = 1;
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app_wr_en_n = 0;
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app_req_wr_n = 1;
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app_req_addr = Address[29:2];
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app_req_len = wrdfifo.size;
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// wait for app_req_ack == 1
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do begin
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@ (posedge sdram_clk);
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end while(app_req_ack == 1'b0);
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@ (negedge sdram_clk);
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app_req = 0;
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for(j=0; j < wrdfifo.size; j++) begin
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wait(app_rd_valid == 1);
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if(app_rd_data !== wrdfifo[j]) begin
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$display("READ ERROR: Burst-No: %d Addr: %x Rxp: %x Exd: %x",j,Address+(j*2),app_rd_data,wrdfifo[j]);
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ErrCnt = ErrCnt+1;
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end else begin
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$display("READ STATUS: Burst-No: %d Addr: %x Rxd: %x",j,Address+(j*2),app_rd_data);
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end
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@ (posedge sdram_clk);
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@ (negedge sdram_clk);
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end
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end
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endtask
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endmodule
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