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[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] [tb_top.sv] - Diff between revs 37 and 38

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Rev 37 Rev 38
Line 113... Line 113...
`else  // 8 BIT SDRAM
`else  // 8 BIT SDRAM
   sdrc_top #(.SDR_DW(8),.SDR_BW(1)) u_dut(
   sdrc_top #(.SDR_DW(8),.SDR_BW(1)) u_dut(
`endif
`endif
      // System
      // System
`ifdef SDR_32BIT
`ifdef SDR_32BIT
          .sdr_width          (2'b00              ), // 32 BIT SDRAM
          .cfg_sdr_width      (2'b00              ), // 32 BIT SDRAM
`elsif SDR_16BIT
`elsif SDR_16BIT
          .sdr_width          (2'b01              ), // 16 BIT SDRAM
          .cfg_sdr_width      (2'b01              ), // 16 BIT SDRAM
`else
`else
          .sdr_width          (2'b10              ), // 8 BIT SDRAM
          .cfg_sdr_width      (2'b10              ), // 8 BIT SDRAM
`endif
`endif
          .cfg_colbits        (2'b00              ), // 8 Bit Column Address
          .cfg_colbits        (2'b00              ), // 8 Bit Column Address
 
 
/* WISH BONE */
/* WISH BONE */
          .wb_rst_i           (!RESETN            ),
          .wb_rst_i           (!RESETN            ),

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