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[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] [tb_top.sv] - Diff between revs 39 and 43

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Rev 39 Rev 43
Line 8... Line 8... 
////  SDRAM CTRL definitions.                                     ////
 
////  SDRAM CTRL definitions.                                     ////
 
////                                                              ////
 
////                                                              ////
 
////  To Do:                                                      ////
 
////  To Do:                                                      ////
 
////    nothing                                                   ////
 
////    nothing                                                   ////
 
////                                                              ////
 
////                                                              ////
 
 
 
//   Version  :0.1 - Test Bench automation is improvised with     ////
 
 
 
//             seperate data,address,burst length fifo.           ////
 
 
 
//             Now user can create different write and            ////
 
 
 
//             read sequence                                      ////
 
 
 
//                                                                ////
 
////  Author(s):                                                  ////
 
////  Author(s):                                                  ////
 
////      - Dinesh Annayya, dinesha@opencores.org                 ////
 
////      - Dinesh Annayya, dinesha@opencores.org                 ////
 
////                                                              ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
////                                                              ////
Line 211... Line 216... 
          .Dqm                (sdr_dqm            )
 
          .Dqm                (sdr_dqm            )
 
     );
 
     );
 
`endif
 
`endif
 
 
 
 
 
//--------------------
 
//--------------------
 
// Write/Read Burst FIFO
 
// data/address/burst length FIFO
 
//--------------------
 
//--------------------
 
int wrdfifo[$]; // write data fifo
 
int dfifo[$]; // data fifo
 
int rddfifo[$]; // read data fifo
 
int afifo[$]; // address  fifo
 
 
 
int bfifo[$]; // Burst Length fifo
 
 
 
 
 
reg [31:0] read_data;
 
reg [31:0] read_data;
 
reg [31:0] ErrCnt;
 
reg [31:0] ErrCnt;
 
int k;
 
int k;
 
reg [31:0] StartAddr;
 
reg [31:0] StartAddr;
Line 246... Line 252... 
  #1000;
 
  #1000;
 
  wait(u_dut.sdr_init_done == 1);
 
  wait(u_dut.sdr_init_done == 1);
 
 
 
 
 
  #1000;
 
  #1000;
 
 
 
 
 
  wrdfifo.push_back(32'h00112233);
 
 
 
  wrdfifo.push_back(32'h11223344);
 
 
 
  wrdfifo.push_back(32'h22334455);
 
 
 
  wrdfifo.push_back(32'h33445566);
 
 
 
  wrdfifo.push_back(32'h44556677);
 
 
 
  wrdfifo.push_back(32'h55667788);
 
 
 
  wrdfifo.push_back(32'h66778899);
 
 
 
  wrdfifo.push_back(32'h77889900);
 
 
 
  wrdfifo.push_back(32'h88990011);
 
 
 
  wrdfifo.push_back(32'h99001122);
 
 
 
 
 
 
 
  burst_write(32'h40000);
 
  burst_write(32'h4_0000,8'h4);
 
 #1000;
 
 #1000;
 
  burst_read(32'h40000);
 
  burst_read();
 
 
 
 
 
 #1000;
 
 #1000;
 
  burst_write(32'h7000_0000);
 
  burst_write(32'h0040_0000,8'h5);
 
 #1000;
 
 #1000;
 
  burst_read(32'h7000_0000);
 
  burst_read();
 
 
 
 
 
 
 
  // 4 Write & 4 Read
 
 
 
  burst_write(32'h4_0000,8'h4);
 
 
 
  burst_write(32'h5_0000,8'h5);
 
 
 
  burst_write(32'h6_0000,8'h6);
 
 
 
  burst_write(32'h7_0000,8'h7);
 
 
 
  burst_read();
 
 
 
  burst_read();
 
 
 
  burst_read();
 
 
 
  burst_read();
 
 
 
 
 
 
 
 
 
 
 
  // 2 write and 2 read random
 
 
 
 
 
  for(k=0; k < 20; k++) begin
 
  for(k=0; k < 20; k++) begin
 
     StartAddr = $random & 32'h07FFFFFF;
 
     StartAddr = $random & 32'h003FFFFF;
 
     burst_write(StartAddr);
 
     burst_write(StartAddr,($random & 8'h3f)+1);
 
    #1000;
 
 #100;
 
     burst_read(StartAddr);
 
 
 
 
 
     StartAddr = $random & 32'h003FFFFF;
 
 
 
     burst_write(StartAddr,($random & 8'h3f)+1);
 
 
 
 #100;
 
 
 
     burst_read();
 
 
 
 #100;
 
 
 
     burst_read();
 
 
 
 #100;
 
  end
 
  end
 
 
 
 
 
 
 
 
 
  #10000;
 
  #10000;
 
 
 
 
Line 288... Line 304... 
    $finish;
 
    $finish;
 
end
 
end
 
 
 
 
 
task burst_write;
 
task burst_write;
 
input [31:0] Address;
 
input [31:0] Address;
 
 
 
input [7:0]  bl;
 
int i;
 
int i;
 
begin
 
begin
 
 
 
  afifo.push_back(Address);
 
 
 
  bfifo.push_back(bl);
 
 
 
 
 
   @ (negedge sys_clk);
 
   @ (negedge sys_clk);
 
   $display("Write Address: %x, Burst Size: %d",Address,wrdfifo.size);
 
   $display("Write Address: %x, Burst Size: %d",Address,bl);
 
 
 
 
 
   for(i=0; i < wrdfifo.size; i++) begin
 
   for(i=0; i < bl; i++) begin
 
      wb_stb_i        = 1;
 
      wb_stb_i        = 1;
 
      wb_cyc_i        = 1;
 
      wb_cyc_i        = 1;
 
      wb_we_i         = 1;
 
      wb_we_i         = 1;
 
      wb_sel_i        = 4'b1111;
 
      wb_sel_i        = 4'b1111;
 
      wb_addr_i       = Address[31:2]+i;
 
      wb_addr_i       = Address[31:2]+i;
 
      wb_dat_i        = wrdfifo[i];
 
      wb_dat_i        = $random & 32'hFFFFFFFF;
 
 
 
      dfifo.push_back(wb_dat_i);
 
 
 
 
 
      do begin
 
      do begin
 
          @ (posedge sys_clk);
 
          @ (posedge sys_clk);
 
      end while(wb_ack_o == 1'b0);
 
      end while(wb_ack_o == 1'b0);
 
          @ (negedge sys_clk);
 
          @ (negedge sys_clk);
Line 314... Line 335... 
   wb_cyc_i           = 0;
 
   wb_cyc_i           = 0;
 
end
 
end
 
endtask
 
endtask
 
 
 
 
 
task burst_read;
 
task burst_read;
 
input [31:0] Address;
 
reg [31:0] Address;
 
 
 
reg [7:0]  bl;
 
 
 
 
 
int i,j;
 
int i,j;
 
reg [31:0]   rd_data;
 
reg [31:0]   exp_data;
 
begin
 
begin
 
 
 
 
 
 
 
   Address = afifo.pop_front();
 
 
 
   bl      = bfifo.pop_front();
 
   @ (negedge sys_clk);
 
   @ (negedge sys_clk);
 
 
 
 
 
      for(j=0; j < wrdfifo.size; j++) begin
 
      for(j=0; j < bl; j++) begin
 
         wb_stb_i        = 1;
 
         wb_stb_i        = 1;
 
         wb_cyc_i        = 1;
 
         wb_cyc_i        = 1;
 
         wb_we_i         = 0;
 
         wb_we_i         = 0;
 
         wb_addr_i       = Address[31:2]+j;
 
         wb_addr_i       = Address[31:2]+j;
 
 
 
 
 
 
 
         exp_data        = dfifo.pop_front(); // Exptected Read Data
 
         do begin
 
         do begin
 
             @ (posedge sys_clk);
 
             @ (posedge sys_clk);
 
         end while(wb_ack_o == 1'b0);
 
         end while(wb_ack_o == 1'b0);
 
         if(wb_dat_o !== wrdfifo[j]) begin
 
         if(wb_dat_o !== exp_data) begin
 
             $display("READ ERROR: Burst-No: %d Addr: %x Rxp: %x Exd: %x",j,wb_addr_i,wb_dat_o,wrdfifo[j]);
 
             $display("READ ERROR: Burst-No: %d Addr: %x Rxp: %x Exd: %x",j,wb_addr_i,wb_dat_o,exp_data);
 
             ErrCnt = ErrCnt+1;
 
             ErrCnt = ErrCnt+1;
 
         end else begin
 
         end else begin
 
             $display("READ STATUS: Burst-No: %d Addr: %x Rxd: %x",j,wb_addr_i,wb_dat_o);
 
             $display("READ STATUS: Burst-No: %d Addr: %x Rxd: %x",j,wb_addr_i,wb_dat_o);
 
         end
 
         end
 
         @ (negedge sdram_clk);
 
         @ (negedge sdram_clk);

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