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https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk
[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] [tb_top.sv] - Diff between revs 44 and 45
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| Rev 44 |
Rev 45 |
| Line 164... |
Line 164... |
.cfg_sdr_trp_d (4'h2 ),
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.cfg_sdr_trp_d (4'h2 ),
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.cfg_sdr_trcd_d (4'h2 ),
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.cfg_sdr_trcd_d (4'h2 ),
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.cfg_sdr_cas (3'h3 ),
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.cfg_sdr_cas (3'h3 ),
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.cfg_sdr_trcar_d (4'h7 ),
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.cfg_sdr_trcar_d (4'h7 ),
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.cfg_sdr_twr_d (4'h1 ),
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.cfg_sdr_twr_d (4'h1 ),
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.cfg_sdr_rfsh (12'hC35 ),
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.cfg_sdr_rfsh (12'h100 ), // reduced from 12'hC35
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.cfg_sdr_rfmax (3'h6 )
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.cfg_sdr_rfmax (3'h6 )
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);
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);
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| Line 257... |
Line 257... |
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burst_write(32'h4_0000,8'h4);
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burst_write(32'h4_0000,8'h4);
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#1000;
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#1000;
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burst_read();
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burst_read();
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// Repeat one more time to analysis the
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// SDRAM state change for same col/row address
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burst_write(32'h4_0000,8'h4);
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#1000;
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#1000;
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#1000;
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burst_write(32'h0040_0000,8'h5);
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burst_write(32'h0040_0000,8'h5);
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#1000;
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#1000;
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burst_read();
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burst_read();
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// 4 Write & 4 Read
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// 4 Write & 4 Read
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burst_write(32'h4_0000,8'h4);
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burst_write(32'h4_0000,8'h4);
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