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[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] [tb_top.sv] - Diff between revs 56 and 68

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Rev 56 Rev 68
Line 76... Line 76...
//--------------------------------------
//--------------------------------------
// Wish Bone Interface
// Wish Bone Interface
// -------------------------------------
// -------------------------------------
reg             wb_stb_i           ;
reg             wb_stb_i           ;
wire            wb_ack_o           ;
wire            wb_ack_o           ;
reg  [24:0]     wb_addr_i          ;
reg  [25:0]     wb_addr_i          ;
reg             wb_we_i            ; // 1 - Write, 0 - Read
reg             wb_we_i            ; // 1 - Write, 0 - Read
reg  [dw-1:0]   wb_dat_i           ;
reg  [dw-1:0]   wb_dat_i           ;
reg  [dw/8-1:0] wb_sel_i           ; // Byte enable
reg  [dw/8-1:0] wb_sel_i           ; // Byte enable
wire  [dw-1:0]  wb_dat_o           ;
wire  [dw-1:0]  wb_dat_o           ;
reg             wb_cyc_i           ;
reg             wb_cyc_i           ;
Line 102... Line 102...
   wire [7:0]           Dq                 ; // SDRAM Read/Write Data Bus
   wire [7:0]           Dq                 ; // SDRAM Read/Write Data Bus
   wire [0:0]           sdr_dqm            ; // SDRAM DATA Mask
   wire [0:0]           sdr_dqm            ; // SDRAM DATA Mask
`endif
`endif
 
 
wire [1:0]            sdr_ba             ; // SDRAM Bank Select
wire [1:0]            sdr_ba             ; // SDRAM Bank Select
wire [11:0]           sdr_addr           ; // SDRAM ADRESS
wire [12:0]           sdr_addr           ; // SDRAM ADRESS
wire                  sdr_init_done      ; // SDRAM Init Done
wire                  sdr_init_done      ; // SDRAM Init Done
 
 
// to fix the sdram interface timing issue
// to fix the sdram interface timing issue
wire #(2.0) sdram_clk_d   = sdram_clk;
wire #(2.0) sdram_clk_d   = sdram_clk;
 
 
Line 173... Line 173...
 
 
 
 
`ifdef SDR_32BIT
`ifdef SDR_32BIT
mt48lc2m32b2 #(.data_bits(32)) u_sdram32 (
mt48lc2m32b2 #(.data_bits(32)) u_sdram32 (
          .Dq                 (Dq                 ) ,
          .Dq                 (Dq                 ) ,
          .Addr               (sdr_addr           ),
          .Addr               (sdr_addr[11:0]     ),
          .Ba                 (sdr_ba             ),
          .Ba                 (sdr_ba             ),
          .Clk                (sdram_clk_d        ),
          .Clk                (sdram_clk_d        ),
          .Cke                (sdr_cke            ),
          .Cke                (sdr_cke            ),
          .Cs_n               (sdr_cs_n           ),
          .Cs_n               (sdr_cs_n           ),
          .Ras_n              (sdr_ras_n          ),
          .Ras_n              (sdr_ras_n          ),
Line 188... Line 188...
 
 
`elsif SDR_16BIT
`elsif SDR_16BIT
 
 
   IS42VM16400K u_sdram16 (
   IS42VM16400K u_sdram16 (
          .dq                 (Dq                 ),
          .dq                 (Dq                 ),
          .addr               (sdr_addr           ),
          .addr               (sdr_addr[11:0]     ),
          .ba                 (sdr_ba             ),
          .ba                 (sdr_ba             ),
          .clk                (sdram_clk_d        ),
          .clk                (sdram_clk_d        ),
          .cke                (sdr_cke            ),
          .cke                (sdr_cke            ),
          .csb                (sdr_cs_n           ),
          .csb                (sdr_cs_n           ),
          .rasb               (sdr_ras_n          ),
          .rasb               (sdr_ras_n          ),
Line 203... Line 203...
`else
`else
 
 
 
 
mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (
mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (
          .Dq                 (Dq                 ) ,
          .Dq                 (Dq                 ) ,
          .Addr               (sdr_addr           ),
          .Addr               (sdr_addr[11:0]     ),
          .Ba                 (sdr_ba             ),
          .Ba                 (sdr_ba             ),
          .Clk                (sdram_clk_d        ),
          .Clk                (sdram_clk_d        ),
          .Cke                (sdr_cke            ),
          .Cke                (sdr_cke            ),
          .Cs_n               (sdr_cs_n           ),
          .Cs_n               (sdr_cs_n           ),
          .Ras_n              (sdr_ras_n          ),
          .Ras_n              (sdr_ras_n          ),

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