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https://opencores.org/ocsvn/securehash256bits/securehash256bits/trunk
[/] [securehash256bits/] [trunk/] [sha256compressionCore.vhd] - Diff between revs 4 and 5
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| Rev 4 |
Rev 5 |
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--(Maximum Frequency: 339.997MHz)
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--(Maximum Frequency: 301.051MHz)
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LIBRARY IEEE;
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LIBRARY IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_unsigned.all;
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Line 48... |
h <= g + w + k;
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h <= g + w + k;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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--main_loop_pipe asynchron circuitry
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--main_loop_pipe asynchron circuitry
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su1 <= (temp1(5 downto 0) & temp1(31 downto 6)) xor (temp1(10 downto 0) & temp1(31 downto 11)) xor (temp1(24 downto 0) & temp1(31 downto 25));
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su1 <= (sum(5 downto 0) & sum(31 downto 6)) xor (sum(10 downto 0) & sum(31 downto 11)) xor (sum(24 downto 0) & sum(31 downto 25));
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ch <= (sum and f) xor ((not sum) and g);
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ch <= (sum and f) xor ((not sum) and g);
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su0 <= (temp2(1 downto 0) & temp2(31 downto 2)) xor (temp2(12 downto 0) & temp2(31 downto 13)) xor (temp2(21 downto 0) & temp2(31 downto 22));
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su0 <= (temp2(1 downto 0) & temp2(31 downto 2)) xor (temp2(12 downto 0) & temp2(31 downto 13)) xor (temp2(21 downto 0) & temp2(31 downto 22));
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maj <= (temp2 and (b xor c)) xor (b and c);
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maj <= (temp2 and (b xor c)) xor (b and c);
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sum <= e1 + temp1;
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sum <= e1 + temp1;
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temp2 <= temp1 + a1 + a2;
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temp2 <= temp1 + a1 + a2;
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