URL
https://opencores.org/ocsvn/sha256_hash_core/sha256_hash_core/trunk
Show entire file |
Details |
Blame |
View Log
Rev 9 |
Rev 10 |
Line 12... |
Line 12... |
-- This is the gv_sha256 engine top level.
|
-- This is the gv_sha256 engine top level.
|
-- The gv_sha256 is a stream hash engine, i.e., the data words are hashed as a stream of words read from an input bus, with
|
-- The gv_sha256 is a stream hash engine, i.e., the data words are hashed as a stream of words read from an input bus, with
|
-- control inputs for BEGIN/END of the message data stream. The input bus is a 32bit word bus, with a byte lane selector to signalize
|
-- control inputs for BEGIN/END of the message data stream. The input bus is a 32bit word bus, with a byte lane selector to signalize
|
-- how many bytes are valid in the last word.
|
-- how many bytes are valid in the last word.
|
--
|
--
|
-- It is a structural integration of the logic blocks for the SHA256 engine, with the internal datapath and controlpath wires.
|
-- The core is a structural integration of the logic blocks for the SHA256 engine, with the internal datapath and controlpath wires.
|
--
|
--
|
-- Written in synthesizable VHDL, the hash engine is a low resource, area-efficient implementation of the FIPS-180-4 SHA256 hash algorithm.
|
-- Written in synthesizable VHDL, the hash engine is a low resource, area-efficient implementation of the FIPS-180-4 SHA256 hash algorithm.
|
-- Designed around the core registers and combinational hash functions as a 768bit-wide engine, the engine takes 64+1 clocks to
|
-- Designed around the core registers and combinational hash functions as a 768bit-wide engine, the engine takes 64+1 clocks to
|
-- compute a hash block.
|
-- compute a hash block.
|
--
|
--
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.