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https://opencores.org/ocsvn/sha256_hash_core/sha256_hash_core/trunk
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Rev 10 |
| Line 140... |
Line 140... |
reg_h <= next_reg_h;
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reg_h <= next_reg_h;
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end if;
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end if;
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end if;
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end if;
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end process core_regs_proc;
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end process core_regs_proc;
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--=============================================================================================
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-- COMBINATIONAL LOGIC
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--=============================================================================================
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-- word rotation and bit manipulation for each cycle
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-- input muxes and word shifter wires
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-- input muxes and word shifter wires
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next_reg_a_proc: next_reg_a <= unsigned(A_i) when ld_i = '1' else sum0;
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next_reg_a_proc: next_reg_a <= unsigned(A_i) when ld_i = '1' else sum0;
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next_reg_b_proc: next_reg_b <= unsigned(B_i) when ld_i = '1' else reg_a;
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next_reg_b_proc: next_reg_b <= unsigned(B_i) when ld_i = '1' else reg_a;
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next_reg_c_proc: next_reg_c <= unsigned(C_i) when ld_i = '1' else reg_b;
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next_reg_c_proc: next_reg_c <= unsigned(C_i) when ld_i = '1' else reg_b;
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next_reg_d_proc: next_reg_d <= unsigned(D_i) when ld_i = '1' else reg_c;
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next_reg_d_proc: next_reg_d <= unsigned(D_i) when ld_i = '1' else reg_c;
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