URL
https://opencores.org/ocsvn/socgen/socgen/trunk
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://digilentinc.com"
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xmlns:socgen="http://digilentinc.com"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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digilentinc.com
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digilentinc.com
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Nexys2
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Nexys2
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sram
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sram
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be default
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be
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fs-sim
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fs-sim
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dest_dir../verilog/
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dest_dir../verilog/
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verilogSourcelibraryDir
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verilogSourcelibraryDir
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fs-syn
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fs-syn
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dest_dir../verilog/
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dest_dir../verilog/
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verilogSourcelibraryDir
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verilogSourcelibraryDir
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fs-lint
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fs-lint
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dest_dir../verilog/lint/
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dest_dir../verilog/lint/
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verilogSourcelibraryDir
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verilogSourcelibraryDir
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verilog
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verilog
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cde_sram_be
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ADDR
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8
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WIDTH
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8
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WORDS
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256
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WRITETHRU
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1
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fs-sim
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sim:*Simulation:*
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Verilog
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fs-sim
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syn:*Synthesis:*
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Verilog
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fs-syn
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lintlint
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rtl
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verilog:Kactus2:
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verilog
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Verilog
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sim:*Simulation:*
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fs-lint
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Verilog
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fs-sim
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syn:*Synthesis:*
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Verilog
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fs-syn
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lint:*Lint:*
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Verilog
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fs-lint
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ADDR10
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WIDTH8
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WORDS1024
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WRITETHRU0
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clk
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wire
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in
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cs
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wire
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in
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wr
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wire
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in
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rd
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wire
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in
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be
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wire
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ADDR10
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in
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WIDTH8
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WORDS1024
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WRITETHRU0
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clk
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wire
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in
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cs
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wire
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in
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addr
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wr
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wire
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wire
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in
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in
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ADDR-10
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rd
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wire
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in
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wdata
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be
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wire
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wire
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in
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in
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WIDTH-10
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rdata
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reg
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out
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WIDTH-10
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addr
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wire
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in
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ADDR-10
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wdata
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wire
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in
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WIDTH-10
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rdata
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reg
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out
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WIDTH-10
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