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// You should have received a copy of the GNU Lesser General //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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-->
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-->
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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opencores.org
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opencores.org
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io
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io
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io_timer
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io_timer
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def default
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def
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slave_clk
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slave_clk
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clk
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clk
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clk
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clk
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slave_reset
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slave_reset
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reset
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reset
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reset
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reset
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mb
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mb
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little
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8
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rdata
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rdata
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wire
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70
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addr
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rdata
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addr
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rdata
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30
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wire
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70
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addr
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addr
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30
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wdata
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wdata
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70
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wdata
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wdata
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70
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rd
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rd
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rd
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wr
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rd
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wr
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wr
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cs
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wr
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cs
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cs
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cs
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little
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8
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gen_registers
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102.1
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common
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none
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./tools/regtool/gen_registers
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bus_intf
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mb
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dest_dir
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../verilog
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gen_registers
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102.1
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:*common:*
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none
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tools/regtool/gen_registers
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bus_intf
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mb
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dest_dir
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../verilog
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gen_verilog
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104.0
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none
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common
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./tools/verilog/gen_verilog
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destination
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io_timer_def
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gen_verilog
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104.0
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none
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:*common:*
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tools/verilog/gen_verilog
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destination
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io_timer_def
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fs-common
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../verilog/top.body
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verilogSourcefragment
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fs-common
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../verilog/top.body
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verilogSourcefragment
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fs-sim
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../verilog/copyright.v
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verilogSourceinclude
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fs-sim
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../verilog/common/io_timer_def
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verilogSourcemodule
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mb
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../verilog/io_timer_def_mb
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../verilog/copyright.v
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verilogSourcemodule
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verilogSourceinclude
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../verilog/common/io_timer_def
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verilogSourcemodule
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mb
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../verilog/io_timer_def_mb
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verilogSourcemodule
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verilog
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spirit:library="Testbench"
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spirit:name="toolflow"
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spirit:version="verilog"/>
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verilog
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ipxact:library="Testbench"
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ipxact:name="toolflow"
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ipxact:version="verilog"/>
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commoncommon
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Verilog
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fs-common
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sim:*Simulation:*
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Verilog
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fs-sim
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syn:*Synthesis:*
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common:*common:*
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Verilog
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Verilog
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fs-sim
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fs-common
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sim:*Simulation:*
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Verilog
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fs-sim
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doc
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syn:*Synthesis:*
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Verilog
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spirit:library="Testbench"
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spirit:name="toolflow"
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fs-sim
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spirit:version="documentation"/>
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:*Documentation:*
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Verilog
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doc
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ipxact:library="Testbench"
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ipxact:name="toolflow"
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ipxact:version="documentation"/>
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:*Documentation:*
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Verilog
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TIMERS2
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enable
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wire
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in
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enable
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wire
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in
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clk
|
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wire
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in
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irq
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reg
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out
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TIMERS-10
|
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reset
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wire
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in
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cs
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wire
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in
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rd
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wire
|
mb
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in
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8
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mb
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0x00
|
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wr
|
mb_microbus
|
wire
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0x10
|
in
|
8
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addr
|
timer_0_start
|
wire
|
0x0
|
in
|
8
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30
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read-only
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timer_0_count
|
|
0x2
|
|
8
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read-only
|
|
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wdata
|
timer_0_end
|
wire
|
0x4
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in
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8
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70
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write-only
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|
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|
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rdata
|
timer_1_start
|
wire
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0x8
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out
|
8
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70
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read-only
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timer_1_count
|
|
0xa
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|
8
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read-only
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timer_1_end
|
|
0xc
|
|
8
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write-only
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irq
|
|
reg
|
|
out
|
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TIMERS-10
|
|
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mb
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8
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mb
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0x00
|
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mb_microbus
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0x10
|
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8
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|
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timer_0_start
|
|
0x0
|
|
8
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read-only
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timer_0_count
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0x2
|
|
8
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read-only
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timer_0_end
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0x4
|
|
8
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write-only
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timer_1_start
|
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0x8
|
|
8
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read-only
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timer_1_count
|
|
0xa
|
|
8
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read-only
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timer_1_end
|
|
0xc
|
|
8
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write-only
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