OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [usb_epp/] [rtl/] [xml/] [usb_epp_def.xml] - Diff between revs 134 and 135

Show entire file | Details | Blame | View Log

Rev 134 Rev 135
Line 25... Line 25...
//   You should have received a copy of the GNU Lesser General            //
//   You should have received a copy of the GNU Lesser General            //
//   Public License along with this source; if not, download it           //
//   Public License along with this source; if not, download it           //
//   from http://www.opencores.org/lgpl.shtml                             //
//   from http://www.opencores.org/lgpl.shtml                             //
//                                                                        //
//                                                                        //
-->
-->
 
 
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
 
opencores.org
opencores.org
logic
logic
usb_epp
usb_epp
def  default
def
 
 
 
 
 
 
 
 
 
 
 slave_clk
 slave_clk
  
  
  
  
  
      
    
  
      
    
        clk
      
        clk
        clk
      
        clk
    
      
 
    
 
          
 
      
 
  
 
 
 
 
 
 
 slave_reset
 slave_reset
  
  
  
  
  
      
    
  
      
    
        reset
      
        reset
        reset
      
        reset
    
      
 
    
 
          
 
      
 
 
 
  
 
 
 
 
 
 
 
 
 
 
 
 
  gen_verilog
 
  104.0
 
  none
 
  common
 
  ./tools/verilog/gen_verilog
 
  
 
    
 
      destination
 
      usb_epp_def
 
    
 
  
 
 
 
 
 
 
 
 
 
 
 
 
  gen_verilog
 
  104.0
 
  none
 
  :*common:*
 
  tools/verilog/gen_verilog
 
  
 
    
 
      destination
 
      usb_epp_def
 
    
 
  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
       
 
 
 
              
 
              verilog
 
              
 
              
 
                                   spirit:library="Testbench"
 
                                   spirit:name="toolflow"
 
                                   spirit:version="verilog"/>
 
              
 
              
 
 
 
 
 
 
       
 
 
 
              
 
              verilog
 
              
 
              
 
                                   ipxact:library="Testbench"
 
                                   ipxact:name="toolflow"
 
                                   ipxact:version="verilog"/>
 
              
 
              
 
 
 
 
 
 
              
 
              commoncommon
 
 
 
              Verilog
 
              
 
                     
 
                            fs-common
 
                     
 
              
 
 
 
 
              
 
              common:*common:*
 
 
 
              Verilog
 
              
 
                     
 
                            fs-common
 
                     
 
              
 
 
              
 
              sim:*Simulation:*
 
 
 
              Verilog
 
              
 
                     
 
                            fs-sim
 
                     
 
              
 
 
 
              
              
              syn:*Synthesis:*
              sim:*Simulation:*
 
 
              Verilog
              Verilog
              
              
                     
                     
                            fs-syn
                            fs-sim
                     
                     
              
              
 
 
 
              
 
              syn:*Synthesis:*
 
 
              
              Verilog
              doc
              
              
                     
              
                            fs-syn
                                   spirit:library="Testbench"
                     
                                   spirit:name="toolflow"
              
                                   spirit:version="documentation"/>
 
              
 
              :*Documentation:*
 
              Verilog
 
              
 
 
 
 
 
      
              
 
              doc
 
              
 
              
 
                                   ipxact:library="Testbench"
 
                                   ipxact:name="toolflow"
 
                                   ipxact:version="documentation"/>
 
              
 
              :*Documentation:*
 
              Verilog
 
              
 
 
 
 
 
      
 
 
 
 
 
 
 
 
eppastb_in
 
wire
 
in
 
 
 
 
 
eppdstb_in
 
wire
 
in
 
 
 
 
 
usbflag_in
clk
wire
wire
in
in
 
 
 
 
eppwait_out
reset
wire
wire
out
in
 
 
 
 
eppwait_in
 
wire
 
in
 
 
 
 
 
eppwait_oe
 
wire
 
out
 
 
 
 
 
usbwr_out
eppastb_in
wire
wire
out
in
 
 
 
 
usbwr_oe
eppdstb_in
wire
wire
out
in
 
 
 
 
usbwr_in
usbflag_in
wire
wire
in
in
 
 
 
 
usbmode_out
eppwait_out
wire
wire
out
out
 
 
 
 
usbmode_oe
eppwait_in
wire
wire
out
in
 
 
 
 
usbmode_in
eppwait_oe
wire
wire
in
out
 
 
 
 
usboe_out
usbwr_out
wire
wire
out
out
 
 
 
 
usboe_oe
usbwr_oe
wire
wire
out
out
 
 
 
 
usboe_in
usbwr_in
wire
wire
in
in
 
 
 
 
usbadr_out
usbmode_out
wire
wire
out
out
10
 
 
 
 
 
usbadr_oe
usbmode_oe
wire
wire
out
out
 
 
 
 
usbadr_in
usbmode_in
wire
wire
in
in
10
 
 
 
 
 
usbpktend_out
usboe_out
wire
wire
out
out
 
 
 
 
usbpktend_oe
usboe_oe
wire
wire
out
out
 
 
 
 
usbpktend_in
usboe_in
wire
wire
in
in
 
 
 
 
usbdir_out
usbadr_out
wire
wire
out
out
 
10
 
 
 
 
usbdir_oe
usbadr_oe
wire
wire
out
out
 
 
 
 
usbdir_in
usbadr_in
wire
wire
in
in
 
10
 
 
 
 
eppdb_in
usbpktend_out
wire
wire
in
out
70
 
 
 
 
 
eppdb_out
usbpktend_oe
wire
wire
out
out
70
 
 
 
 
 
eppdb_oe
usbpktend_in
wire
wire
out
in
 
 
 
 
eppwr_in
usbdir_out
wire
wire
in
out
 
 
 
 
usbclk_out
usbdir_oe
wire
wire
out
out
 
 
 
 
usbclk_oe
usbdir_in
wire
wire
out
in
 
 
 
 
usbclk_in
eppdb_in
wire
wire
in
in
 
70
 
 
 
 
usbrdy_in
eppdb_out
wire
wire
in
out
 
70
 
 
 
 
 
eppdb_oe
 
wire
 
out
 
 
 
 
 
eppwr_in
 
wire
 
in
 
 
 
 
 
usbclk_out
 
wire
 
out
 
 
 
 
 
usbclk_oe
 
wire
 
out
 
 
 
 
 
usbclk_in
 
wire
 
in
 
 
 
 
 
usbrdy_in
 
wire
 
in
 
 
 
 
 
 
 
 
 
 
  
 
 
 
    
 
      fs-common
 
 
 
      
 
        
 
        ../verilog/top.body
 
        verilogSourcefragment
 
      
 
 
 
 
 
    
 
 
 
 
 
 
  
 
 
 
    
 
      fs-common
 
 
 
      
 
        
 
        ../verilog/top.body
 
        verilogSourcefragment
 
      
 
 
    
 
      fs-sim
 
 
 
      
    
        
 
        ../verilog/copyright
 
        verilogSourceinclude
 
      
 
 
 
      
 
        
 
        ../verilog/common/usb_epp_def
 
        verilogSourcemodule
 
      
 
 
 
 
 
 
 
      
 
        dest_dir
 
        ../views/sim/
 
        verilogSourcelibraryDir
 
      
 
 
 
 
    
 
      fs-sim
 
 
 
      
 
        
 
        ../verilog/copyright
 
        verilogSourceinclude
 
      
 
 
    
      
 
        
 
        ../verilog/common/usb_epp_def
 
        verilogSourcemodule
 
      
 
 
 
 
 
 
 
      
 
        dest_dir
 
        ../views/sim/
 
        verilogSourcelibraryDir
 
      
 
 
 
 
    
 
      fs-syn
 
 
 
      
    
        
 
        ../verilog/copyright
 
        verilogSourceinclude
 
      
 
 
 
      
 
        
 
        ../verilog/common/usb_epp_def
 
        verilogSourcemodule
 
      
 
 
 
 
 
 
 
      
 
        dest_dir
 
        ../views/syn/
 
        verilogSourcelibraryDir
 
      
 
 
 
 
    
 
      fs-syn
 
 
    
      
 
        
 
        ../verilog/copyright
 
        verilogSourceinclude
 
      
 
 
 
      
 
        
 
        ../verilog/common/usb_epp_def
 
        verilogSourcemodule
 
      
 
 
 
 
 
 
 
      
 
        dest_dir
 
        ../views/syn/
 
        verilogSourcelibraryDir
 
      
 
 
  
 
 
 
 
    
 
 
 
 
 
 
 
 
 
 
 
  
 
 
 
 
 
 
 
 
 
 
 
 
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.